- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄26800 > MC74AC00M (ON SEMICONDUCTOR) AC SERIES, QUAD 2-INPUT NAND GATE, PDSO14 PDF資料下載
參數(shù)資料
| 型號： | MC74AC00M |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 門電路 |
| 英文描述： | AC SERIES, QUAD 2-INPUT NAND GATE, PDSO14 |
| 封裝： | EIAJ, PLASTIC, 14 PIN |
| 文件頁數(shù)： | 29/45頁 |
| 文件大小： | 434K |
| 代理商： | MC74AC00M |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當(dāng)前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁
http://onsemi.com
39
Figure 1–52. I/O Pin Internal Structure
VCC
IIN
IOZ
CLAMP DIODES
INPUT
OUTPUT
The pin is either an input or an output. When testing the
ICC of the device, the pins selected as outputs by the T/R
signal must either be enabled and left open or be disabled
and tied to either rail. If the output device is disabled and
allowed to float, the input device will also float, and an
excessive amount of current will flow from VCC to ground.
A simple rule to follow is to treat any output which is
disabled as an input. This will help insure the integrity of an
ICC test.
Another area which might precipitate problems is the
measurement of the leakages on I/O pins. The I/O pin
internal structure is depicted below.
The pin is internally connected to both an input device and
an output device; the limit for a leakage test must be the
combined IIN specification of the input and the IOZ
specification of the output. For FACT devices, IIN is
specified at
±1 A while IOZ is specified at ±5 A.
Combining these gives a limit of
±6 A for I/O pins. Usually,
I/O pins will show leakages that are less than the IOZ
specification of the output alone.
Testing CMOS circuits is no more difficult than testing
their bipolar counterparts. However, there are some areas of
concern that will be new to many test engineers beginning
to work with CMOS. Becoming familiar with and
understanding these areas of concern prior to creating a test
philosophy will avert many problems that might otherwise
arise later.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC74AC04MR1 | AC SERIES, HEX 1-INPUT INVERT GATE, PDSO14 |
| MC74AC05MR2 | AC SERIES, HEX 1-INPUT INVERT GATE, PDSO14 |
| MC74ACT05DT | ACT SERIES, HEX 1-INPUT INVERT GATE, PDSO14 |
| MC74AC109N | AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| MC74AC109D | AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC74AC00MEL | 功能描述:邏輯門 2-6V Quad 2-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74AC00MELG | 功能描述:邏輯門 2-6V Quad 2-Input NAND RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74AC00ML1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74AC00MR1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74AC00N | 功能描述:邏輯門 2-6V Quad 2-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。