參數(shù)資料
型號： MC74AC00M
廠商： ON SEMICONDUCTOR
元件分類： 門電路
英文描述： AC SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝： EIAJ, PLASTIC, 14 PIN
文件頁數(shù)： 14/45頁
文件大?。?/td> 434K
代理商： MC74AC00M
http://onsemi.com
25
should not induce a switch condition on the appropriate
outputs of the FACT device.
Good high frequency wiring practices should be used in
constructing test jigs. Leads on the load capacitor should be
as short as possible to minimize ripples on the output wave
form transitions and to minimize undershoot. Generous
ground metal (preferably a ground plane) should be used for
the same reasons. A VCC bypass capacitor should be
provided at the test socket, also with minimum lead lengths.
Rise and Fall Times
Input signals should have rise and fall times of 3 ns and
signal swing of 0 V to 3.0 V VCC for ‘ACT devices or 0 V
to VCC for ‘AC devices. Rise and fall times less than or equal
to 1 ns should be used for testing fmax or pulse widths.
CMOS devices, including 4000 Series CMOS, HC, HCT
and FACT families, tend to oscillate when the input rise and
fall times become lengthy. As a direct result of its increased
performance, FACT devices can be more sensitive to slow
input rise and fall times than other lower performance
technologies.
It is important to understand why this oscillation occurs.
Consider the outputs, where the problem is initiated.
Usually, CMOS outputs drive capacitive loads with low DC
leakage. When the output changes from a HIGH level to a
LOW level, or from a LOW level to a HIGH level, this
capacitance has to be charged or discharged. With the
present high performance technologies, this charging or
discharging takes place in a very short time, typically 2–3 ns.
The requirement to charge or discharge the capacitive loads
quickly creates a condition where the instantaneous current
change through the output structure is quite high. A voltage
is generated across the VCC or ground leads inside the
package due to the inductance of these leads. The internal
ground of the chip will change in reference to the outside
world because of this induced voltage.
Consider the input. If the internal ground changes, the
input voltage level appears to change to the DUT. If the input
rise time is slow enough, its level might still be in the device
threshold region, or very close to it, when the output
switches. If the internally-induced voltage is large enough,
it is possible to shift the threshold region enough so that it
re-crosses the input level. If the gain of the device is
sufficient and the input rise or fall time is slow enough, then
the device may go into oscillation. As device propagation
delays become shorter, the inputs will have less time to rise
or fall through the threshold region. As device gains
increase, the outputs will swing more, creating more
induced voltage. Instantaneous current change will be
greater as outputs become quicker, generating more induced
voltage.
Package-related causes of output oscillation are not
entirely to blame for problems with input rise and fall time
measurements. All testers have VCC and ground leads with
a finite inductance. This inductance needs to be added to the
inductance in the package to determine the overall voltage
which will be induced when the outputs change. As the
reference for the input signals moves further away from the
pin under test, the test will be more susceptible to problems
caused by the inductance of the leads and stray noise. Any
noise on the input signal will also cause problems. With
FACT logic having gains as high as 100, it merely takes a 50
mV change in the input to generate a full 5 V swing on the
output.
*Vmi = 50% VCC for ‘AC devices; 1.5 V for ‘ACT devices
Vmo = 50% for ‘AC/‘ACT devices
DATA
IN
DATA
OUT
tpxx
Vmi
Vmo
Figure 1–23. Waveform for Inverting and
Non-Inverting Functions
CONTROL
IN
CLOCK
OUTPUT
Vmi
trec
Vmi
tPLH
Vmo
tPHL
Vm
tw
Figure 1–24. Propagational Delay, Pulse Width
and trec Waveforms
相關(guān)PDF資料
PDF描述
MC74AC04MR1 AC SERIES, HEX 1-INPUT INVERT GATE, PDSO14
MC74AC05MR2 AC SERIES, HEX 1-INPUT INVERT GATE, PDSO14
MC74ACT05DT ACT SERIES, HEX 1-INPUT INVERT GATE, PDSO14
MC74AC109N AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
MC74AC109D AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC74AC00MEL 功能描述:邏輯門 2-6V Quad 2-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
MC74AC00MELG 功能描述:邏輯門 2-6V Quad 2-Input NAND RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
MC74AC00ML1 制造商:Rochester Electronics LLC 功能描述:- Bulk
MC74AC00MR1 制造商:Rochester Electronics LLC 功能描述:- Bulk
MC74AC00N 功能描述:邏輯門 2-6V Quad 2-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
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