參數(shù)資料
型號(hào)： MC68HC705P6ACDW
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 8/98頁(yè)
文件大?。?/td> 0K
描述： IC MCU 2.1MHZ 4.5K OTP 28-SOIC
標(biāo)準(zhǔn)包裝： 26
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 21
程序存儲(chǔ)器容量： 4.5KB（4.5K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 176 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
General Description
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
16
Freescale Semiconductor
1.3.2.1 Crystal
The circuit in Figure 1-2(a) shows a typical oscillator circuit for an AT-cut, parallel resonant crystal. Follow
the crystal manufacturer’s recommendations, as the crystal parameters determine the external
component values required to provide maximum stability and reliable startup. The load capacitance
values used in the oscillator circuit design should include all stray capacitances. Mount the crystal and
components as close as possible to the pins for startup stabilization and to minimize output distortion.
1.3.2.2 Ceramic Resonator
In cost-sensitive applications, use a ceramic resonator in place of a crystal. Use the circuit in Figure 1-2(a)
for a ceramic resonator and follow the resonator manufacturer’s recommendations, as the resonator
parameters determine the external component values required for maximum stability and reliable starting.
The load capacitance values used in the oscillator circuit design should include all stray capacitances.
Mount the resonator and components as close as possible to the pins for startup stabilization and to
minimize output distortion.
1.3.2.3 External Clock
An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the
OSC2 input not connected, as shown in Figure 1-2(b).
1.3.3 RESET
Driving this input low will reset the MCU to a known startup state. The RESET pin contains an internal
Schmitt trigger to improve its noise immunity. Refer to Chapter 4 Resets.
1.3.4 PA0–PA7
These eight I/O pins comprise port A. The state of any pin is software programmable and all port A lines
are configured as inputs during power-on or reset. Port A has mask-option register enabled interrupt
capability with internal pullup devices selectable for any pin. Refer to Chapter 6 Input/Output Ports.
1.3.5 PB5/SDO, PB6/SDI, and PB7/SCK
These three I/O pins comprise port B and are shared with the SIOP communications subsystem. The
state of any pin is software programmable, and all port B lines are configured as inputs during power-on
1.3.6 PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/VREFH
These eight I/O pins comprise port C and are shared with the A/D converter subsystem. The state of any
pin is software programmable and all port C lines are configured as inputs during power-on or reset. Refer
1.3.7 PD5 and PD7/TCAP
These two I/O pins comprise port D and one of them is shared with the 16-bit timer subsystem. The state
of PD5 is software programmable and is configured as an input during power-on or reset. PD7 is always
an input. It may be read at any time, regardless of which mode of operation the 16-bit timer is in. Refer to
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MC68HC705P6ADW 制造商:Rochester Electronics LLC 功能描述:MCU, 176 BYTES RAM, A/D - Bulk
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MC68HC705P6CDW 制造商:Motorola Inc 功能描述:
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