參數(shù)資料
型號: MC68HC705P6ACDW
廠商: Freescale Semiconductor
文件頁數(shù): 30/98頁
文件大?。?/td> 0K
描述: IC MCU 2.1MHZ 4.5K OTP 28-SOIC
標(biāo)準(zhǔn)包裝: 26
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 4.5KB(4.5K x 8)
程序存儲器類型: OTP
RAM 容量: 176 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
Interrupts
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
36
Freescale Semiconductor
5.2.3.3 Output Compare Interrupt
The output compare interrupt is generated by a 16-bit timer as described in Chapter 8 Capture/Compare
Timer. The output compare interrupt flag is located in register TSR and its corresponding enable bit can
be found in register TCR. The I bit in the CCR must be clear for the output compare interrupt to be
enabled. The interrupt service routine address is specified by the contents of memory locations $1FF8
and $1FF9.
5.2.3.4 Timer Overflow Interrupt
The timer overflow interrupt is generated by the 16-bit timer as described in Chapter 8 Capture/Compare
Timer. The timer overflow interrupt flag is located in register TSR and its corresponding enable bit can be
found in register TCR. The I bit in the CCR must be clear for the timer overflow interrupt to be enabled.
This internal interrupt will vector to the interrupt service routine located at the address specified by the
contents of memory locations $1FF8 and $1FF9.
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