參數(shù)資料
型號: MC68HC705P6ACDW
廠商: Freescale Semiconductor
文件頁數(shù): 60/98頁
文件大?。?/td> 0K
描述: IC MCU 2.1MHZ 4.5K OTP 28-SOIC
標(biāo)準(zhǔn)包裝: 26
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 4.5KB(4.5K x 8)
程序存儲器類型: OTP
RAM 容量: 176 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
63
Chapter 11
Mask Option Register (MOR)
11.1 Introduction
The mask option register (MOR) contains two bytes of EPROM used to enable or disable each of the
features controlled by mask options on the MC68HC05P6 (a ROM version of the MC68HC705P6A).
The seven programmable options on the MC68HC705P6A are:
1.
COP watchdog timer (enable or disable)
2.
IRQ triggering (edge- or edge- and level-sensitive)
3.
SIOP data bit order (most significant bit or least significant bit first)
4.
SIOP clock rate (OSC divided by 8, 16, 32, or 64)
5.
Stop instruction mode (stop mode or halt mode)
6.
Secure EPROM from external reading
7.
Keyscan interrupt/pullups on PA0–PA7
11.2 Mask Option Register
Mask options are programmed into the mask option register (MOR) by the firmware in the bootloader
ROM. See Figure 11-1.
COP — COP Watchdog Enable
Setting the COP bit will enable the COP watchdog timer. The COP will reset the MCU if the timeout
period is reached before the COP watchdog timer is cleared by the application software and the
voltage applied to the IRQ/VPP pin is between VSS and VDD. Clearing the COP bit will disable the COP
watchdog timer regardless of the voltage applied to the IRQ/VPP pin.
Address: $1EFF
Bit 7
654321
Bit 0
Read:
PA7PU
PA6PU
PA5PU
PA4PU
PA3PU
PA2PU
PA1PU
PA0PU
Write:
Erased State:
00000000
Address: $1F00
Bit 7
654321
Bit 0
Read:
SECURE
SWAIT
SPR1
SPR0
LSBF
LEVEL
COP
Write:
Erased State:
00000000
= Unimplemented
Figure 11-1. Mask Option Register (MOR)
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