參數(shù)資料
型號(hào): MC68HC705P6ACDW
廠商: Freescale Semiconductor
文件頁數(shù): 46/98頁
文件大小: 0K
描述: IC MCU 2.1MHZ 4.5K OTP 28-SOIC
標(biāo)準(zhǔn)包裝: 26
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 21
程序存儲(chǔ)器容量: 4.5KB(4.5K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 176 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
Capture/Compare Timer
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
50
Freescale Semiconductor
8.3.5 Input Capture Registers
When a selected edge occurs on the TCAP pin, the current high and low bytes of the 16-bit counter are
latched into the input capture registers. Reading ICRH before reading ICRL inhibits further capture until
ICRL is read. Reading ICRL after reading the status register clears the input capture flag (ICF). Writing to
the input capture registers has no effect.
NOTE
To prevent interrupts from occurring between readings of ICRH and ICRL,
set the interrupt flag in the condition code register before reading ICRH, and
clear the flag after reading ICRL.
8.3.6 Output Compare Registers
When the value of the 16-bit counter matches the value in the output compare registers, the planned
TCMP pin action takes place. Writing to OCRH before writing to OCRL inhibits timer compares until OCRL
is written. Reading or writing to OCRL after the timer status register clears the output compare flag (OCF).
Address:
ICRH — $0014
Bit 7
654321
Bit 0
Read:
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
Write:
Unaffected by reset
Address:
ICRL — $0015
Bit 7
654321
Bit 0
Write:
Unaffected by reset
= Unimplemented
Figure 8-6. Input Capture Registers (ICRH and ICRL)
Address:
OCRH — $0016
Bit 7
654321
Bit 0
Write:
OCRH7
OCRH6
OCRH5
OCRH4
OCRH3
OCRH2
OCRH1
OCRH0
Read:
Unaffected by reset
Address:
OCRL — $0017
Bit 7
654321
Bit 0
Read:
Unaffected by reset
Figure 8-7. Output Compare Registers (OCRH and OCRL)
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