參數(shù)資料
型號: MC68HC705J1ACP
廠商: Freescale Semiconductor
文件頁數(shù): 143/162頁
文件大?。?/td> 0K
描述: IC MCU 4MHZ 1.2K OTP 20-DIP
標(biāo)準包裝: 18
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 14
程序存儲器容量: 1.2KB(1.2K x 8)
程序存儲器類型: OTP
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
Low-Power Modes
Effects of Stop and Wait Modes
MC68HC705J1A — Rev. 4.0
Technical Data
Low-Power Modes
COP watchdog reset — A timeout of the COP watchdog resets the
MCU, starts the CPU clock, and loads the program counter with
the contents of locations $07FE and $07FF. Software can enable
timer interrupts so that the MCU periodically can exit wait mode to
reset the COP watchdog.
Timer interrupt — Real-time interrupt requests and timer overflow
interrupt requests start the MCU clock and load the program
counter with the contents of locations $07F8 and $07F9.
5.4 Effects of Stop and Wait Modes
The STOP and WAIT instructions have the effects described in this
subsection on MCU modules.
5.4.1 Clock Generation
The STOP instruction:
The STOP instruction disables the internal oscillator, stopping the
CPU clock and all peripheral clocks.
After exiting stop mode, the CPU clock and all enabled peripheral
clocks begin running after the oscillator stabilization delay.
NOTE:
The oscillator stabilization delay holds the MCU in reset for the first 4064
internal clock cycles.
The WAIT instruction:
The WAIT instruction disables the CPU clock.
After exiting wait mode, the CPU clock and all enabled peripheral
clocks immediately begin running.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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