參數(shù)資料
型號(hào): MC68HC705J1ACP
廠商: Freescale Semiconductor
文件頁數(shù): 142/162頁
文件大?。?/td> 0K
描述: IC MCU 4MHZ 1.2K OTP 20-DIP
標(biāo)準(zhǔn)包裝: 18
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 14
程序存儲(chǔ)器容量: 1.2KB(1.2K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
Technical Data
MC68HC705J1A — Rev. 4.0
Low-Power Modes
Low-Power Modes
Enabling halt mode prevents the computer operating properly
(COP) watchdog from being inadvertently turned off by a STOP
instruction.
Data-retention mode — In data-retention mode, the MCU retains
RAM contents and CPU register contents at VDD voltages as low
as 2.0 Vdc. The data-retention feature allows the MCU to remain
in a low power-consumption state during which it retains data, but
the CPU cannot execute instructions.
5.3 Exiting Stop and Wait Modes
The events described in this subsection bring the MCU out of stop mode
and load the program counter with the reset vector or with an interrupt
vector.
Exiting stop mode:
External reset — A logic 0 on the RESET pin resets the MCU,
starts the CPU clock, and loads the program counter with the
contents of locations $07FE and $07FF.
External interrupt — A high-to-low transition on the IRQ/VPP pin or
a low-to-high transition on an enabled port A external interrupt pin
starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
Exiting wait mode:
External reset — A logic 0 on the RESET pin resets the MCU,
starts the CPU clock, and loads the program counter with the
contents of locations $07FE and $07FF.
External interrupt — A high-to-low transition on the IRQ/VPP pin or
a low-to-high transition on an enabled port A external interrupt pin
starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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