參數(shù)資料
型號(hào): MC68HC705J1ACP
廠商: Freescale Semiconductor
文件頁數(shù): 100/162頁
文件大?。?/td> 0K
描述: IC MCU 4MHZ 1.2K OTP 20-DIP
標(biāo)準(zhǔn)包裝: 18
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 14
程序存儲(chǔ)器容量: 1.2KB(1.2K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
Technical Data
MC68HC705J1A — Rev. 4.0
Memory
Memory
SWAIT — Stop-to-Wait Conversion Bit
The SWAIT bit enables halt mode. When the SWAIT bit is set, the
CPU interprets the STOP instruction as a WAIT instruction, and the
MCU enters halt mode. Halt mode is the same as wait mode, except
that an oscillator stabilization delay of 1 to 4064 tcyc occurs after
exiting halt mode.
1 = Halt mode enabled
0 = Halt mode not enabled
SWPDI — Software Pulldown Inhibit Bit
The SWPDI bit inhibits software control of the I/O port pulldown
devices. The SWPDI bit overrides the pulldown inhibit bits in the port
pulldown inhibit registers.
1 = Software pulldown control inhibited
0 = Software pulldown control not inhibited
PIRQ — Port A External Interrupt Bit
The PIRQ bit enables the PA0–PA3 pins to function as external
interrupt pins.
1 = PA0–PA3 enabled as external interrupt pins
0 = PA0–PA3 not enabled as external interrupt pins
LEVEL —External Interrupt Sensitivity Bit
The LEVEL bit controls external interrupt triggering sensitivity.
1 = External interrupts triggered by active edges and active levels
0 = External interrupts triggered only by active edges
COPEN — COP Enable Bit
The COPEN bit enables the COP watchdog.
1 = COP watchdog enabled
0 = COP watchdog disabled
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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