參數(shù)資料
型號(hào)： MC68HC11F1CFN4R2
廠商： Freescale Semiconductor
文件頁數(shù)： 68/158頁
文件大?。?/td> 0K
描述： IC MCU 1K RAM 4MHZ 68-PLCC
標(biāo)準(zhǔn)包裝： 1
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 4MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 30
程序存儲(chǔ)器類型： ROMless
EEPROM 大?。?/td> 512 x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-LCC（J 形引線）
包裝： 剪切帶 (CT)
其它名稱： MC68HC11F1CFN4RCT
PIN DESCRIPTIONS
TECHNICAL DATA
2-3
2.2 Reset (RESET)
An active low bidirectional control signal, RESET, acts as an input to initialize the MCU
to a known start-up state. It also acts as an open-drain output to indicate that an inter-
nal failure has been detected in either the clock monitor or COP watchdog circuit. The
CPU distinguishes between internal and external reset conditions by sensing whether
the reset pin rises to a logic one in less than two E-clock cycles after a reset has oc-
curred. It is not advisable to connect an external resistor-capacitor (RC) power-up de-
lay circuit to the reset pin of M68HC11 devices because the circuit charge time
constant can cause the device to misinterpret the type of reset that occurred. Refer to
SECTION 5 RESETS AND INTERRUPTS for further information.
Figure 2-3 illustrates a reset circuit that uses an external switch. Other circuits can be
used, however, it is important to incorporate a low voltage interrupt (LVI) circuit to pre-
vent operation at insufficient voltage levels which could result in erratic behavior or cor-
ruption of RAM.
Figure 2-3 External Reset Circuit
2.3 E-Clock Output (E)
E is the output connection for the internally generated E clock. The signal from E is
used as a timing reference. The frequency of the E-clock output is one fourth that of
the input frequency at the EXTAL pin. When E-clock output is low, an internal process
is taking place. When it is high, data is being accessed. All clocks, including the E
clock, are halted when the MCU is in STOP mode. The E clock can be turned off in
single-chip modes to reduce the effects of radio frequency interference (RFI). Refer to
2.4 Crystal Driver and External Clock Input (XTAL, EXTAL)
These two pins provide the interface for either a crystal or a CMOS-compatible clock
to control the internal clock generator circuitry. Either a crystal oscillator or a CMOS
compatible clock can be used. The resulting E-clock rate is the input frequency divided
by four.
MANUAL
RESET SWITCH
4.7 k
TO RESET
OF M68HC11
4.7 k
VDD
MC34064
IN
GND
2
3
1
RESET
1.0
F
4.7 k
VDD
MC34164
IN
GND
2
3
1
RESET
OPTIONAL POWER-ON DELAY
AND MANUAL RESET SWITCH
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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