參數(shù)資料
型號： MC68HC11F1CFN4R2
廠商： Freescale Semiconductor
文件頁數(shù)： 128/158頁
文件大小： 0K
描述： IC MCU 1K RAM 4MHZ 68-PLCC
標(biāo)準(zhǔn)包裝： 1
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 4MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 30
程序存儲器類型： ROMless
EEPROM 大小： 512 x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-LCC（J 形引線）
包裝： 剪切帶 (CT)
其它名稱： MC68HC11F1CFN4RCT
RESETS AND INTERRUPTS
TECHNICAL DATA
5-9
For some interrupt sources, such as the SCI interrupts, the flags are automatically
cleared during the normal course of responding to the interrupt requests. For example,
the RDRF flag in the SCI system is cleared by the automatic clearing mechanism con-
sisting of a read of the SCI status register while RDRF is set, followed by a read of the
SCI data register. The normal response to an RDRF interrupt request would be to read
the SCI status register to check for receive errors, then to read the received data from
the SCI data register. These two steps satisfy the automatic clearing mechanism with-
out requiring any special instructions.
5.4.1 Interrupt Recognition and Register Stacking
An interrupt can be recognized at any time after it is enabled by its local mask, if any,
and by the global mask bit in the CCR. Once an interrupt source is recognized, the
CPU responds at the completion of the instruction being executed. Interrupt latency
varies according to the number of cycles required to complete the current instruction.
When the CPU begins to service an interrupt, the contents of the CPU registers are
pushed onto the stack in the order shown in Table 5-5. After the CCR value is stacked,
the I bit and the X bit (if XIRQ is pending) are set to inhibit further interrupts. The inter-
rupt vector for the highest priority pending source is fetched, and execution continues
Table 5-4 Interrupt and Reset Vector Assignments
Vector Address
Interrupt Source
CCR
Mask Bit
Local Mask
FFC0, C1 – FFD4, D5
Reserved
—
FFD6, D7
SCI Serial System
I
SCI Receive Data Register Full
RIE
SCI Receiver Overrun
RIE
SCI Transmit Data Register Empty
TIE
SCI Transmit Complete
TCIE
SCI Idle Line Detect
ILIE
FFD8, D9
SPI Serial Transfer Complete
I
SPIE
FFDA, DB
Pulse Accumulator Input Edge
I
PAII
FFDC, DD
Pulse Accumulator Overflow
I
PAOVI
FFDE, DF
Timer Overflow
I
TOI
FFE0, E1
Timer Input Capture 4/Output Compare 5
I
I4/O5I
FFE2, E3
Timer Output Compare 4
I
OC4I
FFE4, E5
Timer Output Compare 3
I
OC3I
FFE6, E7
Timer Output Compare 2
I
OC2I
FFE8, E9
Timer Output Compare 1
I
OC1I
FFEA, EB
Timer Input Capture 3
I
IC3I
FFEC, ED
Timer Input Capture 2
I
IC2I
FFEE, EF
Timer Input Capture 1
I
IC1I
FFF0, F1
Real-Time Interrupt
I
RTII
FFF2, F3
IRQ
I
None
FFF4, F5
XIRQ Pin
X
None
FFF6, F7
Software Interrupt
None
FFF8, F9
Illegal Opcode Trap
None
FFFA, FB
COP Failure
None
NOCOP
FFFC, FD
Clock Monitor Fail
None
CME
FFFE, FF
RESET
None
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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