參數(shù)資料
型號： MC68HC11F1CFN4R2
廠商： Freescale Semiconductor
文件頁數(shù)： 53/158頁
文件大小： 0K
描述： IC MCU 1K RAM 4MHZ 68-PLCC
標準包裝： 1
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 4MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 30
程序存儲器類型： ROMless
EEPROM 大?。?/td> 512 x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-LCC（J 形引線）
包裝： 剪切帶 (CT)
其它名稱： MC68HC11F1CFN4RCT
ELECTRICAL CHARACTERISTICS
MC68HC11F1
A-12
TECHNICAL DATA
NOTES:
1. Input clocks with duty cycles other than 50% affect bus performance.
2. Indicates a parameter affected by clock stretching. Add n(tcyc) to parameter value, where:
n = 1, 2, or 3 depending on values written to CSSTRH register.
3. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
Table A-7 Expansion Bus Timing
VDD = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH
Num
Characteristic
Symbol
2.0 MHz
3.0 MHz
4.0 MHz
Unit
Min
Max
Min
Max
Min
Max
Frequency of Operation (E-Clock Frequency)
fo
dc
2.0
dc
3.0
dc
4.0
MHz
1
Cycle Time
tcyc = 1/fo
tcyc
500
—
333
—
250
—
ns
2
Pulse Width, E Low
PWEL = 1/2 tcyc – 20 ns
PWEL
230
—
147
—
105
—
ns
3
Pulse Width, E High
PWEH = 1/2 tcyc – 25 ns
(Note 2)
PWEH
225
—
142
—
100
—
ns
4A
4B
E Clock
Rise Time
Fall Time
tr
tf
—
20
—
20
18
—
20
15
ns
9
Address Hold Time
tAH = 1/8 tcyc – 10 ns
tAH
53—32—21—
ns
11
Address Delay Time
tAD = 1/8 tcyc + 40 ns
tAD
—
103
—82—71
ns
12
Address Valid Time to E Rise
tAV = PWEL – tAD
tAV
128
—65—34—
ns
17
Read Data Setup Time
tDSR
30—30—20—
ns
18
Read Data Hold Time
tDHR
0—0—0—
ns
19
Write Data Delay Time
tDDW
—40—40—40
ns
21
Write Data Hold Time
tDHW = 1/8 tcyc
tDHW
63—42—31—
ns
29
MPU Address Access Time
tACCA = tcyc – tf – tDSR – tAD
(Note 2)
tACCA
348
—
203
—
144
—
ns
39
Write Data Setup Time
tDSW = PWEH – tDDW
(Note 2)
tDSW
185
—
102
—
60
—
ns
50
E Valid Chip Select Delay Time
tECSD
—40—40—40
ns
51
E Valid Chip Select Access Time
tECSA = PWEH – tECSD – tDSR
(Note 2)
tECSA
155
—72—40—
ns
52
Chip Select Hold Time
tCH
020020020
ns
54
Address Valid Chip Select Delay Time
tACSD = 1/4 tcyc + 40 ns
tACSD
—
165
—
123
—
103
ns
55
Address Valid Chip Select Access Time
tACSA = tcyc – tf – tDSR – tACSD
(Note 2)
tACSA
285
—
162
—
113
—
ns
56
Address Valid to Chip Select Time
tAVCS
10—10—10—
ns
57
Address Valid to Data Three-State Time
tAVDZ
—10—10—10
ns
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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