參數(shù)資料
型號： MC68HC11F1CFN4R2
廠商： Freescale Semiconductor
文件頁數(shù)： 36/158頁
文件大?。?/td> 0K
描述： IC MCU 1K RAM 4MHZ 68-PLCC
標(biāo)準(zhǔn)包裝： 1
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 4MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 30
程序存儲器類型： ROMless
EEPROM 大?。?/td> 512 x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-LCC（J 形引線）
包裝： 剪切帶 (CT)
其它名稱： MC68HC11F1CFN4RCT
ANALOG-TO-DIGITAL CONVERTER
MC68HC11F1
10-6
TECHNICAL DATA
10.4 Channel Assignments
The multiplexer allows the A/D converter to select one of sixteen analog signals. Eight
of these channels correspond to port E input lines, four of the channels are internal
reference points or test functions, and four channels are reserved. Refer to Table 10-
*Used for factory testing
10.5 Single-Channel Operation
There are two types of single-channel operation. When SCAN = 0, the first type, the
single selected channel is converted four consecutive times. The first result is stored
in A/D result register 1 (ADR1), and the fourth result is stored in ADR4. After the fourth
conversion is complete, all conversion activity is halted until a new conversion com-
mand is written to the ADCTL register. In the second type of single-channel operation,
SCAN = 1, conversions continue to be performed on the selected channel with the fifth
conversion being stored in register ADR1 (overwriting the first conversion result), the
sixth conversion overwriting ADR2, and so on.
10.6 Multiple-Channel Operation
There are two types of multiple-channel operation. When SCAN = 0, the first type, a
selected group of four channels is converted one time each. The first result is stored
in A/D result register 1 (ADR1), and the fourth result is stored in ADR4. After the fourth
conversion is complete, all conversion activity is halted until a new conversion com-
mand is written to the ADCTL register. In the second type of multiple-channel opera-
tion, SCAN = 1, conversions continue to be performed on the selected group of
channels with the fifth conversion being stored in register ADR1 (replacing the earlier
conversion result for the first channel in the group), the sixth conversion overwriting
ADR2, and so on.
Table 10-1 A/D Converter Channel Assignments
Channel
Number
Channel
Signal
Result in ADRx if
MULT = 1
1
AN0
ADR1
2
AN1
ADR2
3
AN2
ADR3
4
AN3
ADR4
5
AN4
ADR1
6
AN5
ADR2
7
AN6
ADR3
8
AN7
ADR4
9
Reserved
—
10
Reserved
—
11
Reserved
—
12
Reserved
—
13
VRH*
ADR1
14
VRL*
ADR2
15
(VRH)/2*
ADR3
16
Reserved*
ADR4
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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