參數(shù)資料
型號： MC68HC11F1CFN4R2
廠商： Freescale Semiconductor
文件頁數(shù)： 100/158頁
文件大?。?/td> 0K
描述： IC MCU 1K RAM 4MHZ 68-PLCC
標(biāo)準(zhǔn)包裝： 1
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 4MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 30
程序存儲器類型： ROMless
EEPROM 大小： 512 x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-LCC（J 形引線）
包裝： 剪切帶 (CT)
其它名稱： MC68HC11F1CFN4RCT
OPERATING MODES AND ON-CHIP MEMORY
MC68HC11F1
4-8
TECHNICAL DATA
A normal mode is selected when MODB is logic one during reset. One of three reset
vectors is fetched from address $FFFA–$FFFF, and program execution begins from
the address indicated by this vector. If MODB is logic zero during reset, the special
mode reset vector is fetched from addresses $BFFA–$BFFF and software has access
to special test features. Refer to SECTION 5 RESETS AND INTERRUPTS for infor-
mation regarding reset vectors.
4.3.1.1 HPRIO Register
Bits in the HPRIO register select the highest priority interrupt level, select whether
bootstrap ROM is present, and control visibility of internal reads by the CPU. After re-
set, MDA and SMOD select the operating mode.
*Reset states of RBOOT, SMOD, and MDA bits depend on hardware mode selection. Refer to Table 4-3.
RBOOT — Read Bootstrap ROM
Set to one out of reset in bootstrap mode. Valid while in special modes only. Can be
read anytime. Can only be written in special modes.
0 = Bootloader ROM disabled and not in map
1 = Bootloader ROM enabled and in map at $BF00–$BFFF
SMOD and MDA — Special Mode Select and Mode Select A
The initial value of SMOD is the inverse of the logic level present on the MODB pin at
the rising edge of reset. The initial value of MDA equals the logic level present on the
MODA pin at the rising edge of reset. These two bits can be read at any time. They can
be written at any time in special modes. Neither bit can be written is normal modes.
SMOD cannot be set once it has been cleared. Refer to Table 4-3.
IRV — Internal Read Visibility
IRV can be written at any time in special modes (SMOD = 1). In normal modes (SMOD
= 0) IRV can be written only once. In expanded and test modes, IRV determines
whether internal read visibility is on or off. In single-chip and bootstrap modes, IRV has
no meaning or effect.
0 = No internal read visibility on external bus
1 = Data from internal reads is driven out the external data bus.
PSEL[3:0] — Priority Select Bits [3:0]
HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous
$103C
Bit 7
654321
Bit 0
RBOOT*
SMOD*
MDA*
IRV
PSEL3
PSEL2
PSEL1
PSEL0
RESET:
0
000110
Single Chip
0
100110
Expanded
1
010110
Bootstrap
0
1
110110
Special Test
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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