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Bus Operation
MC68360 USER’S MANUAL
Table 4-5 lists the bytes required on the data bus for read cycles. The entries shown as OPx
are portions of the requested operand that are read during that bus cycle and are defined
by SIZ0, SIZ1, A0, and A1 for the bus cycle. Bytes labeled x are “don’t cares” and are not
required during that read cycle.
Table 4-6 lists the combinations of SIZ0, SIZ1, A0, and A1 and the corresponding pattern of
the data transfer for write cycles from the internal multiplexer of the QUICC to the external
data bus. Bytes labeled x are “don't care.”
Figure 4-4 shows the transfer of a long-word operand to a word port. In the first bus cycle,
the QUICC places the four operand bytes on the external bus. Since the address is long-
word aligned in this example, the multiplexer follows the pattern in the entry of
Table 4-6 cor-
responding to SIZ0, SIZ1, A0, A1 = 0000. The port latches the data on bits D16–D31 of the
data bus, asserts DSACK1 (DSACK0 remains negated), and the QUICC terminates the bus
cycle. It then starts a new bus cycle with SIZ0, SIZ1, A0, A1 = 1010 to transfer the remaining
Table 4-4. Address Offset Encoding
A1
A0
Offset
0
+0 Byte
0
1
+1 Byte
1
0
+2 Bytes
1
+3 Bytes
Table 4-5. Data Bus Requirements for Read Cycles
Transfer
Size
Address
Long-Word Port
External Data Bytes Required
Word Port External
Data Bytes Required
Byte Port
External Data
Bytes Required
SIZ1 SIZ0
A1
A0
D31:D24
D23:D16
D15:D8
D7:D0
D31:D24
D23:D16
D31:D24
Byte
0
1
0
OP3
x
OP3
x
OP3
0
1
0
1
x
OP3
x
OP3
0
1
0
x
OP3
x
OP3
x
OP3
0
1
x
OP3
x
OP3
Word
1
0
OP2
OP3
x
OP2
OP3
OP2
1
0
1
x
OP2
OP3
x
OP2
1
0
1
0
x
OP2
OP3
OP2
OP3
OP2
1
0
1
x
OP2
x
OP2
3 Bytes
1
0
OP1
OP2
OP3
x
OP1
OP2
OP1
1
0
1
x
OP1
OP2
OP3
x
OP1
1
0
x
OP1
OP2
OP1
OP2
OP1
1
x
OP1
x
OP1
Long
Word
0
OP0
OP1
OP2
OP3
OP0
OP1
OP0
0
1
x
OP0
OP1
OP2
x
OP0
0
1
0
x
OP0
OP1
OP0
OP1
OP0
0
1
x
OP0
x
OP0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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