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CPM Interrupt Controller (CPIC)
MC68360 USER’S MANUAL
The following list gives an example of how to find the beginning of the interrupt handler from
the interrupt vector. SCC1 is used as an example.
1. Formulate the 8-bit vector. The three MSBs come from VBA2–VBA0 in the CICR. As-
sume these are programmed to 101b. The five LSBs have a fixed value of 11110b (see
Table 7-22). Thus, the 8-bit vector is 10111110b. This is the value presented on the
bus during an interrupt acknowledge cycle.
2. Multiply by 4 to get the offset address of the vector in the vector table. Thus, the offset
address is 1011111000b = $2F8.
3. Determine the full vector address. In a CPU32+ system, the offset is added to the vec-
tor base register in the CPU32+. Assuming that the vector base register = $80000000,
the final vector address is $800002F8.
4. Determine the location of the interrupt handler. At location $800002F8, the address of
the interrupt handler is stored. If the long word at location $800002F8 contains
$80001000, then the first instruction of the SCC1 interrupt handler will be found at
$80001000.
7.15.5 CPIC Programming Model
The user interfaces with the CPIC via four registers. The CICR defines the overall CPM
interrupt attributes. The CIPR indicates which CPM interrupt sources require interrupt ser-
vice. The CIMR allows the user to prevent any CPM interrupt source from generating an
interrupt request. The CISR allows a fully nested environment capability for interrupt
requests within the CPM interrupt level.
7.15.5.1 CPM INTERRUPT CONFIGURATION REGISTER (CICR). The 24-bit read-write
CICR defines the request level for the CPM interrupts, the priority between the SCCs, the
highest priority interrupt, and the vector base address. The CICR, which can be dynamically
changed by the user, is cleared at reset.
SCdP—SCCd Priority Order
These two bits define which SCC will assert its request in the SCCd priority position. The
user should not program the same SCC to more than one priority position (a, b, c, or d).
These bits may be changed dynamically.
00 = SCC1 will assert its request in the SCCd position.
01 = SCC2 will assert its request in the SCCd position.
10 = SCC3 will assert its request in the SCCd position.
11 = SCC4 will assert its request in the SCCd position.
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SCdP
SCcP
SCbP
SCaP
IRL2
IRL1
IRL0
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VBA1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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