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System Integration Module (SIM60)
MC68360 USER’S MANUAL
The following bits are used for DRAM bank properties:
PGS2–PGS0—Page Size
This attribute determines the page size for the DRAM controller (see
Table 6-9). The page
size is the smallest DRAM size the user needs to support with page mode capability.
For instance, PGS = 001 (256K) should be used for a 32-bit-wide memory composed of
four 256K
× 8 devices, a 16-bit-wide memory composed of two 256K × 8 devices, or six-
teen 256K
× 1 devices. In all cases, the width of the DRAMs is irrelevant.
DPS1–DPS0—DRAM Port Size
This attribute determines the DRAM bank port size (see
Table 6-10). The DRAM controller
asserts the appropriate DSACKx lines according to these bits. If an MC68EC040 access
is performed using this DRAM bank and SPS = 00 or 01, the DRAM controller operates
the same way, but asserts TA instead of DSACK.
NOTES
The internal DRAM address multiplexer and the page logic sup-
port only a port size of 32 bits or 16 bits. An 8-bit DRAM port size
is not allowed.
The DRAM controller does not support an external DSACKx re-
sponse for a bank on which page mode is used. Also, an exter-
nal DSACK response may not occur before RAS is asserted.
Table 6-9. DRAM Page Size
PGS2-PGS0
Address Lines Used
# Address/Page in Page Compare
000
A10-25(32), A9-25(16)
256 Addresses
001
A11-25(32), A10-25(16)
512 Addresses
010
A11-25(32), A10-25(16)
512 Addresses
011
A12-25(32), A11-25(16)
1024 Addresses
100
A12-25(32), A11-25(16)
1024 Addresses
101
A13-25(32), A12-25(16)
2048 Addresses
110
A13-25(32), A12-25(16)
2048 Addresses
110
A14-25(32), A13-25(16)
4096 Addresses
Table 6-10. DRAM Port Size
DPS1–DPS0
Result
00
DRAM Port Size Is 32 Bits
01
DRAM Port Size Is 16 Bits
10
Reserved
11
External DSACKx Support
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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