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IDMA Channels
7-50
MC68360 USER’S MANUAL
Single Address Destination Write
. During the single address destination write cycle, the
source device is controlled by the IDMA handshake signals (DREQx, DACKx, and DONEx).
When the source device requests service from the IDMA channel, the IDMA asserts of
DACKx to allow the source device to drive data onto the data bus. The data is written to the
device or to memory selected by the address in the DAPR, the destination function codes in
the FCR, and the size in the CMR. The data bus is placed in a high-impedance state for this
write cycle. For more details about the IDMA handshake signals, see 7.6.3 Interface Signals.
7.6.4.6.3 Fast-Termination Option. While in the operand transfer phase, the IDMA sup-
ports an option to achieve a transfer in the shortest possible number of clocks (see Figure
7-16).
Figure 7-16. Fast Termination Example
Using the SIM60 chip-select logic, the fast-termination option can be employed to give a fast
bus access of two clock cycles rather than the standard three-cycle access time. The fast-
termination option is described in Section 6 System Integration Module (SIM60) and in Sec-
tion 4 Bus Operation.
If the fast-termination option is used with external request burst mode, an extra IDMA cycle
results on every burst transfer. In the burst mode with fast termination selected, a new cycle
starts even if DREQx negation and DACKx assertion occur simultaneously.
AS
(OUTPUT)
DSACKx
(I/O)
S0
S2
S4
S0
S2
S4
S0
S4
S0
DREQx
(INPUT)
OTHER CYCLE
NOTE: This example shows a fast termination on the write cycle. The fast termination
may occur on the read, write, or both.
CLKO1
IDMA READ
CYCLE STEAL
REQUEST
DACKx
(OUTPUT)
ECO = 0
IDMA
FAST
TERMINATION
WRITE
R/W
(OUTPUT)
DACKx
(OUTPUT)
ECO = 1
PERIPHERAL IS
BEING READ
PERIPHERAL IS
BEING WRITTEN
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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