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Timers
7-20
MC68360 USER’S MANUAL
When working in the cascaded mode, the cascaded TRR, TCR, and TCN should always be
referenced with 32-bit bus cycles.
7.5.2.2 TIMER GLOBAL CONFIGURATION REGISTER (TGCR). The TGCR is a 16-bit,
memory-mapped, read/write register that contains configuration parameters used by all four
timers. It allows starting and stopping any number of timers simultaneously if one bus cycle
is used to access TGCR. The TGCR is cleared by reset.
CAS4—Cascade Timers
0 = Normal Operation.
1 = Timers 3 and 4 are cascaded to form a 32-bit timer.
CAS2—Cascade Timers
0 = Normal Operation.
1 = Timers 1 and 2 are cascaded to form a 32-bit timer.
FRZ—Freeze
0 = The corresponding timer ignores the FREEZE pin.
1 = Halt the corresponding timer if the FREEZE pin is asserted. (The FREEZE pin is
asserted in background debug mode when the CPU32+ is enabled.)
STP —Stop Timer
0 = Normal operation.
1 = Reduce power consumption of the timer. This bit stops all clocks to the timer, ex-
cept the clock from the IMB interface, which allows the user to read and write timer
registers. The clocks to the timer remain stopped until the user clears this bit or a
hardware reset occurs.
RST—Reset Timer
0 = Reset the corresponding timer (a software reset is identical to an external reset).
1 = Enable the corresponding timer if the STP bit is cleared.
GM2—Gate Mode for Pin 2
This bit is only valid if the gate function is enabled in TMR3 or TMR4.
0 = Restart gate mode. The TGATE2 pin is used to enable/disable the count. The fall-
ing edge of TGATE2 enables and restarts the count, and the rising edge of
TGATE2 disables the count.
1 = Normal gate mode. This mode is the same as 0, except the falling edge of TGATE2
does not restart the count value in TCN.
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9876543210
CAS4
FRZ4
STP4
RST4
GM2
FRZ3
STP3
RST3
CAS2
FRZ2
STP2
RST2
GM1
FRZ1
STP1
RST1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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