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IDMA Channels
MC68360 USER’S MANUAL
RCI — RISC Controls IDMA
0 = Single Buffer Mode. The user programs all IDMA registers for each buffer transfer.
1 = Auto buffer or buffer chaining mode. The RISC reconfigures the IDMA channel at
the end of each buffer transfer according to the buffer descriptor ring. The choice
between auto buffer and buffer chaining is made in the buffer descriptor itself.
REQG — Request Generation
The REQG bits define what generates the requests for IDMA activity over the bus.
00 = Internal request at limited rate (limited burst bandwidth) set by BT bits
01 = Internal request at maximum rate (one burst)
10 = External request burst transfer mode (DREQx is level sensitive)
11 = External request cycle steal (DREQx is edge sensitive)
SAPI — SAPR Increment
0 = SAPR is not incremented after each transfer.
1 = SAPR is incremented by one, two, or four after each transfer, according to the
SSIZE bits. (SAPR may be incremented by an amount less than the SSIZE value
at the beginning or end of a block transfer, depending on the source starting ad-
dress or byte count.)
DAPI — DAPR Increment
0 = DAPR is not incremented after each transfer.
1 = DAPR is incremented by one, two, or four after each transfer, according to the
DSIZE bits. (DAPR may be incremented by an amount less than the DSIZE value
at the beginning or end of a block transfer, depending on the destination starting
address or byte count.)
SSIZE — Source Size
The following decoding shows the definitions for the SSIZE bits. The user should set these
bits to the port size of the source (e.g., choose byte for an 8-bit peripheral).
00 = Long word
01 = Byte
10 = Word
11 = Reserved
DSIZE — Destination Size
The following decoding shows the definitions for the DSIZE bits. The user should set
these bits to the port size of the destination (e.g., choose byte for an 8-bit peripheral).
00 = Long word
01 = Byte
10 = Word
11 = Reserved
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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