參數(shù)資料
型號(hào): MC68EC030
廠商: Motorola, Inc.
英文描述: Second-Generation 32-Bit Enhanced Embedded Controller
中文描述: 第二代32位增強(qiáng)型嵌入式控制器
文件頁(yè)數(shù): 5/36頁(yè)
文件大?。?/td> 392K
代理商: MC68EC030
MOTOROLA
MC68EC030 TECHNICAL DATA
Go to: www.freescale.com
5
The ACU contains two access control registers that are used to define memory segments ranging in size
from 16 Mbytes to 2 Gbytes each. Each segment is definable in terms of address, read/write access, and
function code. Each segment can be marked as cacheable or non cacheable to control cache accesses
to that memory space.
PROGRAMMING MODEL
As shown in the programming models (see Figures 3 and 4), the MC68EC030 has 16 32-bit general-
purpose registers, a 32-bit program counter, two 32-bit supervisor stack pointers, a 16-bit status register,
a 32-bit vector base register, two 3-bit alternate function code registers, two 32-bit cache handling
(address and control) registers, and two 32-bit transparent translation registers. Registers D0–D7 are
used as data registers for bit and bit field (1 to 32 bit), byte (8 bit), word (16 bit), long-word (32 bit), and
quad-word (64 bit) operations. Registers A0–A6 and the user, interrupt, and master stack pointers are
address registers that may be used as software stack pointers or base address registers. In addition, the
address registers may be used for word and long-word operations. All 16 general-purpose registers (D0–
D7, A0–A7) can be used as index registers.
31
15
16
0
31
15
16
0
31
0
0
7
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
(USP)
PC
CCR
DATA
REGISTERS
ADDRESS
REGISTERS
USER STACK
POINTER
CONDITION CODE
REGISTER
PROGRAM
COUNTER
7
8
15
0
31
15
16
0
8
Figure 3. User Programming Model
F
Freescale Semiconductor, Inc.
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