參數(shù)資料
型號(hào)： MC68EC030
廠商： Motorola, Inc.
英文描述： Second-Generation 32-Bit Enhanced Embedded Controller
中文描述： 第二代32位增強(qiáng)型嵌入式控制器
文件頁(yè)數(shù)： 13/36頁(yè)
文件大小： 392K
代理商： MC68EC030
MOTOROLA
MC68EC030 TECHNICAL DATA
Go to: www.freescale.com
13
DATA CACHE
The organization of the data cache (see Figure 7) is similar to that of the instruction cache. However, the
tag is composed of the upper 24 address bits, the four valid bits, and all three function code bits, explicitly
specifying the address space associated with each line. The data cache employs a write-through policy
with programmable write allocation of data writes— i.e., if a cache hit occurs on a write cycle, both the data
cache and the external device are updated with the new data. If a write cycle generates a cache miss, the
external device is updated, and a new data cache entry can be replaced or allocated for that address,
depending on the state of the write-allocate (WA) bit in the CACR.
F F F
C C C 3
2 1 0 1
2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
3 2
0
1
9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
COMPARATOR
TAG
1 OF 16
SELECT
VALID
TAG REPLACE
INDEX
TAG
LINE HIT
DATA FROMDATA
CACHE DATA BUS
CACHE CONTROL LOGIC
V
V
V
V
ACCESS ADDRESS
DATA TO EXECUTION
UNIT
ENTRY HIT
A
LONG-WORD
SELECT
CACHE SIZE = 64 (LONG WORDS)
LINE SIZE = 4 (LONG WORDS)
SET SIZE = 1
A A A A A A A A A A A A A A A A A A A A A A A A
Figure 7. On-Chip Data Cache Organization
OPERAND TRANSFER MECHANISM
The MC68EC030 offers three different mechanisms by which data can be transferred into and out of the
chip. Asynchronous bus cycles, compatible with the asynchronous bus on the MC68020 and MC68030,
can transfer data in a minimum of three clock cycles; the amount of data transferred on each cycle is
determined by the dynamic bus sizing mechanism on a cycle-by-cycle basis with the data transfer and size
acknowledge (
DSACKx
) signals. Synchronous bus cycles, compatible with the synchronous bus on the
MC68030, are terminated with the synchronous termination (
STERM)
signal and always transfer 32-bits
of data in a minimum of two clock cycles, increasing the bus bandwidth available for other bus masters,
F
Freescale Semiconductor, Inc.
n
.
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參數(shù)描述
MC68EC030CFE25C 功能描述:微處理器 - MPU 32B ON-CHIP CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MC68EC030FE25B 制造商:Motorola Inc 功能描述:
MC68EC030FE25C 功能描述:微處理器 - MPU 32B ON-CHIP CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MC68EC030FE25CB1 功能描述:IC MPU 32BIT ENH 25MHZ 132-CQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M680x0 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類(lèi)型:32-位 MPC85xx PowerQUICC III 特點(diǎn):- 速度:1.2GHz 電壓:1.1V 安裝類(lèi)型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤(pán)
MC68EC030FE40B 制造商:Motorola Inc 功能描述:
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