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參數(shù)資料
| 型號： | MC68EC030 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Second-Generation 32-Bit Enhanced Embedded Controller |
| 中文描述： | 第二代32位增強(qiáng)型嵌入式控制器 |
| 文件頁數(shù)： | 24/36頁 |
| 文件大?。?/td> | 392K |
| 代理商： | MC68EC030 |
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24
MC68EC030 TECHNICAL DATA
Go to: www.freescale.com
MOTOROLA
0.8 V
2.0 V
NOTE:
4
5
1
2
3
Timng measurements are referenced to and froma low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted.
The voltage swing through this range should start outside and pass through the range so that the rise or fall will be
linear between 0.8 V and 2.0 V.
Figure 10. Clock Input Timing Diagram
AC ELECTRICAL SPECIFICATIONS -- READ AND WRITE CYCLES
(V
CC
=5.0Vdc
±
5%; GND=0 Vdc; temperature in defined ranges; see Figures 11–16)
Num.
Characterstics
25MHz
40 MHz
Unit
Min
Max
Min
Max
6
Clock High to Function Code, Size,
RMC
,
IPEND
,
CIOUT
,
Address Valid
0
20
0
14
ns
6A
Clock High to
ECS
,
OCS
Asserted
0
15
0
10
ns
6B
Function Code, Size,
RMC
,
IPEND
,
CIOUT
, Address Valid to
Negating Edge of
ECS
3
—
3
—
ns
7
Clock High to Function Code Size,
RMC
,
CIOUT
, Address Data
High
Impedance
0
40
0
25
ns
8
Clock High to Function Code Size,
RMC
,
IPEND
,
CIOUT
, Address
Invalid
0
—
0
—
ns
9
Clock Low to
AS
,
DS
Asserted,
CBREQ
Valid
3
18
2
10
ns
9A
1
9B
14
AS
to
DS
Assertion Skew (Read)
-10
10
-6
6
ns
AS
Asserted to
DS
Asserted (Write)
27
—
16
—
ns
10
ECS
Width Asserted
10
—
5
—
ns
10A
10B
7
OCS
Width Asserted
10
—
5
—
ns
ECS
,
OCS
Width Negated
5
—
5
—
ns
11
Function Code, Size,
RMC
,
CIOUT
, Address Valid to
AS
Asserted
(and
DS
Asserted, Read)
7
—
5
—
ns
12
Clock Low to
AS
,
DS
,
CBREQ
Negated
0
18
0
10
ns
12A
Clock Low to
ECS
/
OCS
Negated
0
18
0
12
ns
13
AS
,
DS
Negated to Function Code, Size,
RMC
CIOUT
, Address
Invalid
7
—
3
—
ns
14
AS
(and
DS
Read) Width Asserted (Asynchronous Cycle)
70
—
30
—
ns
14A
11
DS
Width Asserted (Write)
30
—
18
—
ns
14B
AS
(and
DS
, Read) Width Asserted (Synchronous Cycle)
30
—
18
—
ns
15
AS
,
DS
Width Negated
30
—
18
—
ns
F
Freescale Semiconductor, Inc.
n
.
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