參數(shù)資料
型號： MC68EC030
廠商： Motorola, Inc.
英文描述： Second-Generation 32-Bit Enhanced Embedded Controller
中文描述： 第二代32位增強型嵌入式控制器
文件頁數(shù)： 25/36頁
文件大小： 392K
代理商： MC68EC030
MOTOROLA
MC68EC030 TECHNICAL DATA
Go to: www.freescale.com
25
AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES
(Continued)
Num.
Characterstics
25MHz
40 MHz
Unit
Min
Max
Min
Max
15A
8
DS
Negated to
AS
Asserted
25
—
16
—
ns
16
Clock High to
AS
,
DS
, R/
W
,
DBEN
,
CBREQ
High Impedance
—
40
—
25
ns
17
AS
,
DS
Negated to R/
W
Invalid
7
—
3
—
ns
18
Clock High to R/
W
High
0
20
0
14
ns
20
Clock High to R/
W
Low
0
20
0
14
ns
21
R/
W
High to
AS
Asserted
7
—
5
—
ns
22
R/
W
Low to
DS
Asserted (Write)
47
—
24
—
ns
23
Clock High to Data-Out Valid
—
20
—
14
ns
24
25
11
25A
9,11
26
11
Data-Out Valid to Negating Edge of
AS
5
—
3
—
ns
AS
,
DS
Negated to Data-Out Invalid
7
—
3
—
ns
DS
Negated to
DBEN
Negated (Write)
7
—
3
—
ns
Data-Out Valid to
DS
Asserted (Write)
7
—
3
—
ns
27
Data-In Valid to Clock Low (Setup)
2
—
1
—
ns
27A
Late
BERR/HALT
Asserted to Clock Low (Setup)
5
—
3
—
ns
28
12
AS, DS Negated to
DSACKx
,
BERR
,
HALT
,
AVEC
Negated
(Asynchronous Hold)
0
40
0
20
ns
28A
12
Clock Low to
DSACKx
,
BERR
,
HALT
,
AVEC
Negated
(Synchronous Hold)
8
70
6
40
ns
29
12
29A
12
30
12
30A
12
31
2
31A
3
AS
,
DS
Negated to Data-In Invalid (Asynchronous Hold)
0
—
0
—
ns
AS
,
DS
Negated to Data-In High Impedance
—
40
—
25
ns
Clock Low to Data-In Invalid (Synchronous Hold)
8
—
6
—
ns
Clock Low to Data-In High Impedance (Read followed by Write)
—
60
—
30
ns
DSACKx
Asserted to Data-In Valid (Asynchronous Data Setup)
—
28
—
14
ns
DSACKx
Asserted to
DSACKx
Valid (Skew)
—
7
—
3
ns
32
RESET
Input Transition Time
—
1.5
—
1.5
Clks
33
Clock Low to
BG
Asserted
0
20
0
14
ns
34
Clock Low to
BG
Negated
0
20
0
14
Clks
35
BR
Asserted to
BG
Asserted (
RMC
Not Asserted)
1.5
3.5
1.5
3.5
Clks
37
37A
6
BGACK
Asserted to
BG
Negated
1.5
3.5
1.5
3.5
Clks
BGACK
Asserted to
BR
Negated
0
1.5
0
1.5
ns
39
BG
Width Negated
60
—
30
—
ns
39A
BG
Width Asserted
60
—
30
—
ns
40
Clock High to
DBEN
Asserted (Read)
0
20
0
16
ns
41
Clock Low to
DBEN
Negated (Read)
0
20
0
16
ns
42
Clock Low to
DBEN
Asserted (Write)
0
20
0
16
ns
43
Clock High to
DBEN
Negated (Write)
0
20
0
16
ns
F
Freescale Semiconductor, Inc.
n
.
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