參數(shù)資料
型號: MC68EC030
廠商: Motorola, Inc.
英文描述: Second-Generation 32-Bit Enhanced Embedded Controller
中文描述: 第二代32位增強型嵌入式控制器
文件頁數(shù): 17/36頁
文件大?。?/td> 392K
代理商: MC68EC030
MOTOROLA
MC68EC030 TECHNICAL DATA
Go to: www.freescale.com
17
ACCESS CONTROL
Two access control registers are provided on the MC68EC030 to control cachability of accesses for two
independent blocks of memory. Each block can range in size from 16 Mbytes to 2 Gbytes, and is
specified in the corresponding ACx register with a base address, a base mask, function code, function
code mask, and read/write mask. A typical use for an access control register is to designate a block of
memory containing I/O devices as non-cachable.
COPROCESSOR INTERFACE
The coprocessor interface is a mechanism for extending the instruction set of the M68000 Family. The
interface provided on the MC68EC030 is the same as that on the MC68020 and MC68030. Examples of
these extensions are the addition of specialized data operands for the existing data types or, for the case
of floating point, the inclusion of new data types and operations implemented by the
MC68881/MC68882 floating-point coprocessors.
SIGNAL DESCRIPTION
Figure 8 illustrates the functional signal groups, and Table 3 describe the signals and their function.
DSACK0
DSACK1
FUNCTION
CODES
ADDRESS
BUS
DATA
BUS
TRANSFER
SIZE
ASYNCHRONOUS
BUS CONTROL
CACHE
CONTROL
EMULATOR
SUPPORT
SYNCHRONOUS
BUS CONTROL
BUS EXCEPTION
CONTROL
BUS ARBITRATION
CONTROL
INTERRUPT
CONTROL
MC68EC030
FC0–FC2
A0–A31
D0–D31
SIZ0
SIZ1
OCS
ECS
R/W
RMC
AS
DS
DBEN
CIIN
CIOUT
CBREQ
CBACK
GND (14)
CLK
CDIS
STATUS
REFILL
STERM
BERR
HALT
RESET
IPL0
IPL1
IPL2
IPEND
AVEC
BR
BG
BGACK
CC
Figure 8. Functional Signal Groups
F
Freescale Semiconductor, Inc.
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