參數(shù)資料
型號: MC56F8347VVFE
廠商: Freescale Semiconductor
文件頁數(shù): 92/172頁
文件大小: 0K
描述: IC DGTL SIGNAL CTLR 160-MAPBGA
標準包裝: 126
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 76
程序存儲器容量: 136KB(68K x 16)
程序存儲器類型: 閃存
RAM 容量: 6K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 160-BGA
包裝: 托盤
配用: MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
56F8347 Technical Data, Rev.11
26
Freescale Semiconductor
Preliminary
GPIOD0
(CS2)
55
P6
Input/
Output
Input,
pull-up
enabled
Port D GPIO — These six GPIO pins can be individually
programmed as input or output pins.
Chip Select — CS2 - CS7 may be programmed within the
EMI module to act as chip selects for specific areas of the
external memory map.
Depending upon the state of the DRV bit in the EMI Bus
Control Register (BCR), CS2 - CS7 are tri-stated when the
external bus is inactive.
Most designs will want to change the DRV state to DRV = 1
instead of using the default setting.
At reset, these pins are configured as GPIO.
To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOD_PUR register.
Example: GPIOD0, clear bit 0 in the GPIOD_PUR register.
GPIOD1
(CS3)
56
L6
GPIOD2
(CS4)
57
K6
GPIOD3
(CS5)
58
N7
GPIOD4
(CS6)
59
P7
GPIOD5
(CS7)
60
L7
TXD0
(GPIOE0)
4
B1
Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Transmit Data — SCI0 transmit data output
Port E GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOE_PUR register.
RXD0
(GPIOE1)
5
D2
Input
Input/
Output
Input,
pull-up
enabled
Receive Data — SCI0 receive data input
Port E GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOE_PUR register.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
Signal Name
Pin
No.
Ball
No.
Type
State
During
Reset
Signal Description
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