TD0 (GPIOE10) 129 B10 Schmitt Input/ Output Schmitt Input/ Output Input, " />
參數(shù)資料
型號(hào): MC56F8347VVFE
廠商: Freescale Semiconductor
文件頁數(shù): 103/172頁
文件大?。?/td> 0K
描述: IC DGTL SIGNAL CTLR 160-MAPBGA
標(biāo)準(zhǔn)包裝: 126
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 76
程序存儲(chǔ)器容量: 136KB(68K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 6K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 160-BGA
包裝: 托盤
配用: MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
56F8347 Technical Data, Rev.11
36
Freescale Semiconductor
Preliminary
TD0
(GPIOE10)
129
B10
Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
TD0 - 3 — Timer D, Channels 0, 1, 2 and 3
Port E GPIO — These GPIO pins can be individually
programmed as input or output pins.
At reset, these pins default to Timer functionality.
To deactivate the internal pull-up resistor, clear the
appropriate bit of the GPIOE_PUR register. See Part 6.5.6
for details.
TD1
(GPIOE11)
130
A10
TD2
(GPIOE12)
131
D10
TD3
(GPIOE13)
132
E10
IRQA
65
K9
Schmitt
Input
Input,
pull-up
enabled
External Interrupt Request A and B — The IRQA and
IRQB inputs are asynchronous external interrupt requests
during Stop and Wait mode operation. During other
operating modes, they are synchronized external interrupt
requests, which indicate an external device is requesting
service. They can be programmed to be level-sensitive or
negative-edge triggered.
To deactivate the internal pull-up resistor, set the IRQ bit in
the SIM_PUDR register. See Part 6.5.6 for details.
IRQB
66
P9
RESET
98
J14
Schmitt
Input
Input,
pull-up
enabled
Reset — This input is a direct hardware reset on the
processor. When RESET is asserted low, the device is
initialized and placed in the reset state. A Schmitt trigger
input is used for noise immunity. When the RESET pin is
deasserted, the initial chip operating mode is latched from
the EXTBOOT pin. The internal reset signal will be
deasserted synchronous with the internal clocks after a fixed
number of internal clocks.
To ensure complete hardware reset, RESET and TRST
should be asserted together. The only exception occurs in a
debugging environment when a hardware device reset is
required and the JTAG/EOnCE module must not be reset. In
this case, assert RESET but do not assert TRST.
Note: The internal Power-On Reset will assert on initial
power-up.
To deactivate the internal pull-up resistor, set the RESET bit
in the SIM_PUDR register. See Part 6.5.6 for details.
RSTO
97
J13
Output
Reset Output — This output reflects the internal reset state
of the chip.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
Signal Name
Pin
No.
Ball
No.
Type
State
During
Reset
Signal Description
相關(guān)PDF資料
PDF描述
MC56F8147VVFE IC DGTL SIGNAL CTLR 160-MAPBGA
MAC7101MAG40 IC MCU 32BIT FLASH 144-LQFP
KMC9328MX1DVM20 IC MCU I.MX 200MHZ 256-MAPBGA
KMC9328MX1CVM15 IC MCU I.MX 150MHZ 256-PBGA
MC9S12C96CFUER IC MCU 16BIT 4K FLASH 80-QFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC56F8355 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-Bit Digital Signal Controllers
MC56F8355MFG60 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Hybrid Controllers
MC56F8355MFGE 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MC56F8355VFG60 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Hybrid Controllers
MC56F8355VFGE 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 BIT HYBRID CNTRLR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT