VSS 27 J4 Supply
參數(shù)資料
型號： MC56F8347VVFE
廠商： Freescale Semiconductor
文件頁數(shù)： 84/172頁
文件大?。?/td> 0K
描述： IC DGTL SIGNAL CTLR 160-MAPBGA
標準包裝： 126
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 60MHz
連通性： CAN，EBI/EMI，SCI，SPI
外圍設備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 76
程序存儲器容量： 136KB（68K x 16）
程序存儲器類型： 閃存
RAM 容量： 6K x 16
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 3.6 V
數(shù)據(jù)轉換器： A/D 16x12b
振蕩器型： 外部
工作溫度： -40°C ~ 105°C
封裝/外殼： 160-BGA
包裝： 托盤
配用： MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
Signal Pins
56F8347 Technical Data, Rev.11
Freescale Semiconductor
19
Preliminary
VSS
27
J4
Supply
VSS — These pins provide ground for chip logic and I/O
drivers.
VSS
41
K11
VSS
74
G11
VSS
80
E7
VSS
125
J11
VSS
160
E6
VSSA_ADC
115
D12
Supply
ADC Analog Ground — This pin supplies an analog ground
to the ADC modules.
OCR_DIS
91
K14
Input
On-Chip Regulator Disable —
Tie this pin to VSS to enable the on-chip regulator.
Tie this pin to VDD to disable the on-chip regulator.
This pin is intended to be a static DC signal from
power-up to shut down. Do no try to toggle this pin for
power savings during operation.
VCAP1*
62
K8
Supply
VCAP1 - 4 — When OCR_DIS is tied to VSS (regulator
enabled), connect each pin to a 2.2
μF or greater bypass
capacitor in order to bypass the core logic voltage regulator,
required for proper chip operation. When OCR_DIS is tied to
VDD (regulator disabled), these pins become VDD_CORE and
should be connected to a regulated 2.5V power supply.
Note: This bypass is required even if the chip is powered
with an external supply.
VCAP2*
144
E8
VCAP3*
95
H11
VCAP4*
15
G4
* When the on-chip regulator is disabled, these four pins become 2.5V VDD_CORE.
VPP1
141
A7
Input
VPP1 - 2 — These pins should be left unconnected as an
open circuit for normal functionality.
VPP2
2C2
CLKMODE
99
H12
Input
Clock Input Mode Selection — This input determines the
function of the XTAL and EXTAL pins.
1 = External clock input on XTAL is used to directly drive the
input clock of the chip. The EXTAL pin should be grounded.
0 = A crystal or ceramic resonator should be connected
between XTAL and EXTAL.
EXTAL
94
J12
Input
External Crystal Oscillator Input — This input can be
connected to an 8MHz external crystal. Tie this pin low if
XTAL is driven by an external clock source.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
Signal Name
Pin
No.
Ball
No.
Type
State
During
Reset
Signal Description
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