參數(shù)資料
型號(hào)： MC56F8347VVFE
廠商： Freescale Semiconductor
文件頁數(shù)： 110/172頁
文件大?。?/td> 0K
描述： IC DGTL SIGNAL CTLR 160-MAPBGA
標(biāo)準(zhǔn)包裝： 126
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 60MHz
連通性： CAN，EBI/EMI，SCI，SPI
外圍設(shè)備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 76
程序存儲(chǔ)器容量： 136KB（68K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 6K x 16
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 外部
工作溫度： -40°C ~ 105°C
封裝/外殼： 160-BGA
包裝： 托盤
配用： MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
56F8347 Technical Data, Rev.11
42
Freescale Semiconductor
Preliminary
4.3 Interrupt Vector Table
Table 4-5 provides the reset and interrupt priority structure, including on-chip peripherals. The table is
organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. The
priority of an interrupt can be assigned to different levels, as indicated, allowing some control over
interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority
level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA) register. Please see Part
5.6.11 for the reset value of the VBA.
In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the
interrupt vector table. In these instances, the first two locations in the vector table must contain branch or
JMP instructions. All other entries must contain JSR instructions.
Table 4-4 Program Memory Map at Reset
Begin/End
Address
Mode 0 (MA = 0)
Mode 11 (MA = 1)
1. If Flash Security Mode is enabled, EXTBOOT Mode 1 cannot be used. See Security Features, Part 7.
Internal Boot
External Boot
Internal Boot
16-Bit External Address Bus
EMI_MODE = 02,3
16-Bit External Address Bus
2. This mode provides maximum compatibility with 56F80x parts while operating externally.
3. “EMI_MODE = 0”, EMI_MODE pin is tied to ground at boot up.
EMI_MODE = 14
20-Bit External Address Bus
4. “EMI_MODE = 1”, EMI_MODE pin is tied to VDD at boot up.
P:$1F FFFF
P:$10 0000
External Program Memory5
5. Not accessible in reset configuration, since the address is above P$0x00 FFFF. The higher bit address/GPIO (and/or chip
selects) pins must be reconfigured before this external memory is accessible.
External Program Memory5
P:$0F FFFF
P:$03 0000
External Program RAM
COP Reset Address = 02 0002
Boot Location = 02 00006
6. Booting from this external address allows prototyping of the internal Boot Flash.
P:$02 FFFF
P:$02 F800
On-Chip Program RAM
4KB
P:$02 F7FF
P:$02 1000
Reserved
116KB
P:$02 0FFF
P:$02 0000
Boot Flash
8KB
COP Reset Address = 02 0002
Boot Location = 02 0000
Boot Flash
8KB
(Not Used for Boot in this Mode)
P:$01 FFFF
P:$01 0000
External Program RAM5
Internal Program Flash7
128KB
7. The internal Program Flash is relocated in this mode, making it accessible.
P:$00 FFFF
P:$00 0000
Internal Program Flash
128KB
External Program RAM
COP Reset Address = 00 0002
Boot Location = 00 0000
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