參數(shù)資料
型號： MC56F8347VPY60
廠商： MOTOROLA INC
元件分類： 數(shù)字信號處理
英文描述： 16-BIT, 120 MHz, OTHER DSP, PQFP160
封裝： LQFP-160
文件頁數(shù)： 14/160頁
文件大?。?/td> 2217K
代理商： MC56F8347VPY60
110
56F8347 Technical Data
Preliminary
6.5.8.4
GPIO C1 (C1)—Bit 1
This bit selects the alternate function for GPIOC1.
0 = PHASEB1/TB1 (default)
1 = MOSI1
6.5.8.5
GPIO C0 (C0)—Bit 0
This bit selects the alternate function for GPIOC0.
0 = PHASEA1/TB0 (default)
1 = SCLK1
6.5.9
Peripheral Clock Enable Register (SIM_PCE)
The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a
power savings feature. The clocks can be individually controlled for each peripheral on the chip.
Figure 6-12 Peripheral Clock Enable Register (SIM_PCE)
6.5.9.1 External Memory Interface Enable (EMI)—Bit 1
5
Each bit controls clocks to the indicated peripheral.
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.2
Analog-to-Digital Converter B Enable (ADCB)—Bit 14
Each bit controls clocks to the indicated peripheral.
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.3
Analog-to-Digital Converter A Enable (ADCA)—Bit 13
Each bit controls clocks to the indicated peripheral.
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.4
FlexCAN Enable (CAN)—Bit 12
Each bit controls clocks to the indicated peripheral.
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
Base + $C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
EMI
ADCB ADCA
CAN
DEC1
DEC0
TMRD TMRC
TMRB
TMRA
SCI 1
SCI 0
SPI 1
SPI 0
PWMB
PWMA
Write
RESET
11
1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MC56F8347VVF 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
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MC56F8355 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-Bit Digital Signal Controllers
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