參數(shù)資料
型號: MC56F8347VPY60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP160
封裝: LQFP-160
文件頁數(shù): 10/160頁
文件大?。?/td> 2217K
代理商: MC56F8347VPY60
Register Descriptions
568347 Technical Data
107
Preliminary
Figure 6-9 CLKO Select Register (SIM_CLKOSR)
6.5.7.1 Reserved—Bits 1
5–1
0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7.2
Alternate GPIO_B Peripheral Function for A23 (A23)—Bit 9
0 = Peripheral output function of GPIO B[7] is defined to be A[23]
1 = Peripheral output function of GPIO B[7] is defined to be the oscillator_clock (MSTR_OSC, see
6.5.7.3
Alternate GPIO_B Peripheral Function for A22 (A22)—Bit 8
0 = Peripheral output function of GPIO B[6] is defined to be A[22]
1 = Peripheral output function of GPIO B[6] is defined to be SYS_CLK2
6.5.7.4
Alternate GPIO_B Peripheral Function for A21 (A21)—Bit 7
0 = Peripheral output function of GPIO B[5] is defined to be A[21]
1 = Peripheral output function of GPIO B[5] is defined to be SYS_CLK
6.5.7.5
Alternate GPIO_B Peripheral Function for A20 (A20)—Bit 6
0 = Peripheral output function of GPIO B[4] is defined to be A[20]
1 = Peripheral output function of GPIO B[4] is defined to be the prescaler_clock (FREF in
6.5.7.6
Clockout Disable (CLKDIS)—Bit 5
0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL
1 = CLKOUT is tri-stated
6.5.7.7
CLockout Select (CLKOSEL)—Bits 4–0
Selects clock to be muxed out on the CLKO pin.
00000 = SYS_CLK (from OCCS - DEFAULT)
00001 = Reserved for factory test—56800E clock
00010 = Reserved for factory test—XRAM clock
00011 = Reserved for factory test—PFLASH odd clock
00100 = Reserved for factory test—PFLASH even clock
00101 = Reserved for factory test—BFLASH clock
00110 = Reserved for factory test—DFLASH clock
00111 = Oscillator output
01000 = Fout (from OCCS)
Base + $A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
A23
A22
A21
A20
CLK
DIS
CLKOSEL
Write
RESET
0
0000
0
1
0
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