參數(shù)資料
型號: MC56F8347VPY60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP160
封裝: LQFP-160
文件頁數(shù): 11/160頁
文件大?。?/td> 2217K
代理商: MC56F8347VPY60
108
56F8347 Technical Data
Preliminary
01001 = Reserved for factory test—IPB clock
01010 = Reserved for factory test—Feedback (from OCCS, this is path to PLL)
01011 = Reserved for factory test—Prescaler clock (from OCCS)
01100 = Reserved for factory test—Postscaler clock (from OCCS)
01101 = Reserved for factory test—SYS_CLK2 (from OCCS)
01110 = Reserved for factory test—SYS_CLK_DIV2
01111 = Reserved for factory test—SYS_CLK_D
10000 = ADCA clock
10001 = ADCB clock
6.5.8
GPIO Peripheral Select Register (SIM_GPS)
The GPIO Peripheral Select register can be used to multiplex out any one of the three alternate
peripherals for GPIOC. The default peripheral is Quad Decoder 1 and Quad Timer B; these
peripherals work together.
The four I/O pins associated with GPIO C can function as GPIO, Quad Decoder 1/Quad Timer B,
or as SPI 1 signals. GPIO is not the default and is enabled/disabled via the GPIOC_PER, as shown
in Figure 6-10 and Table 6-2. When GPIO C[3:0] are programmed to operate as peripheral I/O,
then the choice between decoder/timer and SPI inputs/outputs is made in the SIM_GPS register and
in conjunction with the Quad Timer Status and Control Registers (SCR). The default state is for
the peripheral function of GPIO C[3:0] to be programmed as decoder functions. This can be
changed by altering the appropriate controls in the indicated registers.
Figure 6-10 Overall Control of Pads Using SIM_GPS Control
GPIOC_PER Register
GPIO Controlled
I/O Pad Control
SIM_ GPS Register
Quad Timer Controlled
SPI Controlled
0
1
0
1
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