參數(shù)資料
型號: MC56F8123
廠商: Motorola, Inc.
英文描述: 16-bit Hybrid Controllers
中文描述: 16位混合控制器
文件頁數(shù): 78/140頁
文件大小: 1981K
代理商: MC56F8123
56F8323 Technical Data, Rev. 11.0
42
Freescale Semiconductor
Preliminary
Table 4-10 Pulse Width Modulator A Registers Address Map
(PWMA_BASE = $00 F140)
PWM is NOT available in the 56F8123 device
Register Acronym
Address Offset
Register Description
PWMA_PMCTRL
$0
Control Register
PWMA_PMFCTRL
$1
Fault Control Register
PWMA_PMFSA
$2
Fault Status Acknowledge Register
PWMA_PMOUT
$3
Output Control Register
PWMA_PMCNT
$4
Counter Register
PWMA_PWMCM
$5
Counter Modulo Register
PWMA_PWMVAL0
$6
Value Register 0
PWMA_PWMVAL1
$7
Value Register 1
PWMA_PWMVAL2
$8
Value Register 2
PWMA_PWMVAL3
$9
Value Register 3
PWMA_PWMVAL4
$A
Value Register 4
PWMA_PWMVAL5
$B
Value Register 5
PWMA_PMDEADTM
$C
Dead Time Register
PWMA_PMDISMAP1
$D
Disable Mapping Register 1
PWMA_PMDISMAP2
$E
Disable Mapping Register 2
PWMA_PMCFG
$F
Configure Register
PWMA_PMCCR
$10
Channel Control Register
PWMA_PMPORT
$11
Port Register
PWMA_PMICCR
$12
Internal Correction Control Register
Table 4-11 Quadrature Decoder 0 Registers Address Map
(DEC0_BASE = $00 F180)
Quadrature Decoder is NOT available in the 56F8123 device
Register Acronym
Address Offset
Register Description
DEC0_DECCR
$0
Decoder Control Register
DEC0_FIR
$1
Filter Interval Register
DEC0_WTR
$2
Watchdog Time-out Register
DEC0_POSD
$3
Position Difference Counter Register
DEC0_POSDH
$4
Position Difference Counter Hold Register
DEC0_REV
$5
Revolution Counter Register
DEC0_REVH
$6
Revolution Hold Register
DEC0_UPOS
$7
Upper Position Counter Register
DEC0_LPOS
$8
Lower Position Counter Register
相關(guān)PDF資料
PDF描述
MC56F8323 16-bit Hybrid Controllers
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