參數(shù)資料
型號: MC56F8123
廠商: Motorola, Inc.
英文描述: 16-bit Hybrid Controllers
中文描述: 16位混合控制器
文件頁數(shù): 112/140頁
文件大?。?/td> 1981K
代理商: MC56F8123
Register Descriptions
56F8323 Technical Data, Rev. 11.0
Freescale Semiconductor
73
Preliminary
5.6.9.8
Timer A, Channel 1 Interrupt Priority Level (TMRA 1 IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10
Interrupt Priority Register 9 (IPR9)
Figure 5-12 Interrupt Priority Register 9 (IPR9)
5.6.10.1
PWM A Fault Interrupt Priority Level (PWMA F IPL)—Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.2
Reserved—Bits 13–12
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.10.3
Reload PWM A Interrupt Priority Level (PWMA_RL IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.4
Reserved—Bits 9–8
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Base + $9
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
PWMA F IPL
0
PWMA_RL
IPL
0
ADCA_ZC IPL
0
ADCA_CC
IPL
0
Write
RESET
000
0000000000000
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參數(shù)描述
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