參數(shù)資料
型號： MC56F8123
廠商： Motorola, Inc.
英文描述： 16-bit Hybrid Controllers
中文描述： 16位混合控制器
文件頁數(shù)： 21/140頁
文件大?。?/td> 1981K
代理商： MC56F8123
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F8323 Technical Data, Rev. 11.0
Freescale Semiconductor
117
Preliminary
10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Note: All address and data buses described here are internal.
Figure 10-5 Asynchronous Reset Timing
Figure 10-6 External Interrupt Timing (Negative Edge-Sensitive)
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and
Stop modes), T = 125ns.
2. Parameters listed are guaranteed by design.
Characteristic
Symbol
Typical
Min
Typical
Max
Unit
See Figure
Minimum RESET Assertion Duration
tRA
16T
—
ns
Edge-sensitive Interrupt Request Width
tIRW
1.5T
—
ns
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
18T
—
ns
tIG - FAST
14T
—
IRQA Width Assertion to Recover from Stop State3
3. The interrupt instruction fetch is visible on the pins only in Mode 3.
tIW
1.5T
—
ns
First Fetch
tRA
tRAZ
tRDA
PAB
PDB
RESET
IRQA
tIRW
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