參數(shù)資料
型號: MC56F8123
廠商: Motorola, Inc.
英文描述: 16-bit Hybrid Controllers
中文描述: 16位混合控制器
文件頁數(shù): 128/140頁
文件大?。?/td> 1981K
代理商: MC56F8123
56F8323 Technical Data, Rev. 11.0
88
Freescale Semiconductor
Preliminary
Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)
6.5.5
Least Significant Half of JTAG ID (SIM_LSH_ID)
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$001D.
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
6.5.6
SIM Pull-up Disable Register (SIM_PUDR)
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these
resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the
appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not
muxed with GPIO). Each bit in the register (see Figure 6-8) corresponds to a functional group of pins. See
Table 2-2 to identify which pins can deactivate the internal pull-up resistor.
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
6.5.6.1
Reserved—Bits 15–12
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.2
RESET—Bit 11
This bit controls the pull-up resistors on the RESET pin.
Base + $6
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
1
0
1
0
Write
RESET
0
0000
0
1
0
1
0
Base + $7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
1
0
1
0
1
Write
RESET
0
0000
0
1
0
1
Base + $8
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
RESET
IRQ
0
JTAG
0
Write
RESET
00
0
相關(guān)PDF資料
PDF描述
MC56F8323 16-bit Hybrid Controllers
MC56MS-14 3500 MHz - 12000 MHz RF/MICROWAVE DOUBLE BALANCED MIXER, 9.5 dB CONVERSION LOSS-MAX
MC56MS-5 3500 MHz - 12000 MHz RF/MICROWAVE DOUBLE BALANCED MIXER, 9.5 dB CONVERSION LOSS-MAX
MC68HC11FC0CFU4 Technical Summary 8-Bit Microcontroller
MC68HC11FC0CFU5 Technical Summary 8-Bit Microcontroller
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