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| 型號： | MC33989DWR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 43/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYSTEM BASE W/CAN 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 控制器類型： | 系統(tǒng)基礎(chǔ)芯片 |
| 接口： | CAN |
| 電源電壓： | 5.5 V ~ 18 V |
| 電流 - 電源： | 45mA |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 剪切帶 (CT) |
| 配用： | KIT33989DWEVB-ND - KIT EVAL 33989DW HS SBC |
| 其它名稱： | MC33989DWR2CT |
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Analog Integrated Circuit Device Data
48
Freescale Semiconductor
33989
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
T1: Is dependent on the selected cyclic sense timing in the TIM2 register (5.0 to 400 ms). LX is sampled
10 s before the end of cyclic sense on time. If the LX correct wake-up level happens just after the sample point, the wake-
up will be detected at the next HS1 activation and a complete period is lost.
T2: It is the same time as LX to VDD1 turn on: typ 100 s
T3 & T4: same as page 42
The total time is 11.5 ms (for a cyclic sense total time of 5.0 ms) in this example.
WAKE-UP TIMING: STOP MODE
The following paragraphs describe the wake-up events from stop mode, and the sequence of the signals at the SBC level. The
wake-up time described is the time from the wake-up event to the SBC INT pin. The wake-up time is the sum of several timings:
wake-up signal detection, the INT pulse, and a minimum delay between INT and SBC ready to operate. At the end of the wake-
up time, the SBC is ready to operate, however the MCU might have already been in a restart operation.
LX Wake-up
Below is the case where the SBC is in stop mode and is awakened by an LX positive edge
T1(L0 high level to INT pulse): typ 100 s.
The total time is 133 s in this case.
Figure 29. Lx Wake-up
CAN Wake-up
The case below describes the signal for CAN wake-up. Refer to page 53 for more details on CAN wake-up signals and the
TCAN analysis.
Figure 30. CAN Wake-up
TCAN
: refer to page 53 for more details.
T1: Third pulse on CAN to INT pulse: typ 80 s.
The total time is 113 s in this case.
CS Wake-up
The figure below describes the wake up from a CS signal transition, while the SBC is in Stop mode.
L0
INT
SBC ready to accept SPI command.
t1
Wake-up signalled to MCU.
tINT + tS-1STSPI (33μs max)
CAN
INT
t1
SBC ready to accept SPI command.
Wake-up signalled to MCU.
tCAN
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| MC33990DR2 | 功能描述:IC TRANSCEIVER J-1850 BUS 8-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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