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參數(shù)資料
| 型號(hào)： | MBM29PL12LM |
| 廠商： | Fujitsu Limited |
| 英文描述： | FLASH MEMORY 128 M (16M ?8/8M ?16) BIT |
| 中文描述： | 快閃記憶體128米（1,600？8/8M？16）位 |
| 文件頁數(shù)： | 28/72頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | MBM29PL12LM |
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MBM29PL12LM
10
28
■
COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
“MBM29PL12LM Standard Command Definitions” in
■
DEVICE BUS OPERATION shows the valid register
command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only
while the Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h)
commands are valid only while the program operation is in progress. Moreover reset commands are functionally
equivalent. Please note that commands must be asserted to DQ
7
to DQ
0
and DQ
15
to DQ
8
bits are ignored.
Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ
5
= 1) to Read mode, the Reset operation
is initiated by writing the reset command sequence into the command register. The devices remain enabled for
reads until the command register contents are altered.
The devices will automatically be in the reset state after power-up. In this case, a command sequence is not
required in order to read data.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore,
manufacture and device codes must be accessible while the devices reside in the target system. PROM pro-
grammers typically access the signature codes by raising A
9
to a high voltage. However applying high voltage
onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming method-
ology. The operation is initiated by writing the Autoselect command sequence into the command register.
The Autoselect command sequence is initiated first by writing two unlock cycles. This is followed by a third write
cycle that contains the address and the Autoselect command. Then the manufacture and device codes can be
read from the address, and an actual data of memory cell can be read from the another address.
Following the command write, a read cycle from address 00h returns the manufactures’s code (Fujitsu = 04h).
A read cycle at address 01h outputs device code. When 227Eh is output, it indicates that two additional codes,
called Extended Device Codes will be required. Therefore the system may continue reading out these Extended
Device Codes at address of 0Eh as well as at 0Fh. Notice that above applies to Word mode. The addresses
and codes differ from those of Byte mode. Refer to “Sector Group Protection Verify Autoselect Codes” in
■
DE-
VICE BUS OPERATION.
To terminate the operation, it is necessary to write the reset command into the register. To execute the Autoselect
command during the operation, reset command must be written before the Autoselect command.
Programming
The devices are programmed on a word-by-word basis. Programming is a 4 bus cycle operation. There are two
“unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are
latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of
CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens first) starts
programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required
to provide further controls. The device will automatically provide adequate internally generated program pulses
and verify the programmed cell margin.
The system can determine the status of the program operation by using DQ
7
(Data Polling), DQ
6
(Toggle Bit) or
RY/BY. The Data Polling and Toggle Bit are automatically performed at the memory location being programmed.
The programming operation is completed when the data on DQ
7
is equivalent to data written to this bit at which
the devices return to the read mode and plogram addresses are no longer latched. Therefore, the devices require
that a valid address to the devices be supplied by the system at this particular instance. Hence Data Polling
requires the same address which is being programmed.
If hardware reset occurs during the programming operation, the data being written is not guaranteed.
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