參數(shù)資料
型號(hào)： MBM29PL12LM10PBT
廠商： Fujitsu Limited
英文描述： FLASH MEMORY 128 M (16M ?8/8M ?16) BIT
中文描述： 快閃記憶體128米（1,600？8/8M？16）位
文件頁數(shù)： 38/72頁
文件大?。?/td> 1036K
代理商： MBM29PL12LM10PBT
MBM29PL12LM
10
38
Word/Byte Configuration
BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the device. When this pin is driven high, the
device operates in the word (16-bit) mode. Data is read and programmed at DQ
15
to DQ
0
. When this pin is driven
low, the device operates in byte (8-bit) mode. In this mode, DQ
15
/A
-1
pin becomes the lowest address bit, and
DQ
14
to DQ
8
bits are High-Z. However, the command bus cycle is always an 8-bit operation and hence commands
are written at DQ
7
to DQ
0
and DQ
15
to DQ
8
bits are ignored.
Data Protection
The device is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transitions. During power up the device automatically reset the internal
state machine in Read mode. Also, with its command register architecture, alteration of memory contents only
occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting form V
CC
power-up
and power-down transitions or system noise.
(1) Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than V
LKO
. If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits are disabled.
Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the V
CC
level
is greater than V
LKO
. It is the user’s responsibility to ensure that the control pins are logically correct to prevent
unintentional writes when V
CC
is above V
LKO
.
If Embedded Erase Algorithm is interrupted, the intervened erasing sector(s) is(are) not valid.
(2) Write Pulse “Glitch” Protection
Noise pulses of less than 3
μ
s (typical) on OE, CE, or WE will not initiate a write cycle.
(3) Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
, or WE = V
IH
. To initiate a write, CE and WE must
be low while OE is high.
(4) Power-up Write Inhibit
Power-up of the devices with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically set to read mode on power-up.
(5) Sector Protection
Device is able to protect each sector group to store and protect data in the user side. Protection circuit voids
both write and erase commands that are addressed to protected sectors.
Any commands to write or erase addressed to protected sector are ignored .
See “Sector Group Protection” in
■
FUNCTIONAL DESCRIPTION.
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