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參數(shù)資料
| 型號： | MBM29PL12LM10PBT |
| 廠商： | Fujitsu Limited |
| 英文描述： | FLASH MEMORY 128 M (16M ?8/8M ?16) BIT |
| 中文描述： | 快閃記憶體128米（1,600？8/8M？16）位 |
| 文件頁數(shù)： | 2/72頁 |
| 文件大小： | 1036K |
| 代理商： | MBM29PL12LM10PBT |
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MBM29PL12LM
10
2
(Continued)
The standard MBM29PL12LM offers access times of 90 ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable (WE),
and output enable (OE) controls.
The MBM29PL12LM supports command set compatible with JEDEC single-power-supply EEPROMS standard.
Commands are written into the command register. The register contents serve as input to an internal state-
machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and
data needed for the programming and erase operations. Reading data out of the devices is similar to reading
from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29PL12LM is programmed by executing the program command sequence. This will invoke the Em-
bedded Program Algorithm
TM
which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Erase is accomplished by executing the erase command sequence. This will
invoke the Embedded Erase Algorithm
TM
which is an internal algorithm that automatically preprograms the array
if it is not already programmed before executing the erase operation. During erase, the device automatically
times the erase pulse widths and verifies proper cell margin.
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. All sectors are erased when shipped from the factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
. Once the end of a program or erase cycle has been completed, the devices
internally return to the read mode.
Fujitsu Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The devices electrically erase all bits within a sector simulta-
neously via hot-hole assisted erase. The words are programmed one word at a time using the EPROM program-
ming mechanism of hot electron injection.
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PDF描述 |
|---|---|
| MBM29PL12LM10PCN | FLASH MEMORY 128 M (16M ?8/8M ?16) BIT |
| MBM30LV0064-PFTN | 64M (8M X 8) BIT NAND-type |
| MBM30LV0064-PFTR | 64M (8M X 8) BIT NAND-type |
| MBM30LV0032 | 32M (4M X 8) BIT NAND-type |
| MBM30LV0032-PFTN | 32M (4M X 8) BIT NAND-type |
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| MBM30035001 | 制造商:LG Corporation 功能描述:Card,Technical |
| MBM30035015 | 制造商:LG Corporation 功能描述:Card,Technical |
| MBM300A6 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:IGBT MODULE RANGE WITH SOFT AND FAST (SFD) FREE-WHEELING DIODES |
| MBM300GR12A | 制造商:n/a 功能描述:IGBT Module |
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