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參數(shù)資料
| 型號： | MB9BF505RPMC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120 |
| 文件頁數(shù)： | 8/120頁 |
| 文件大小： | 1277K |
| 代理商： | MB9BF505RPMC |
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105
8266D-MCU Wireless-06/12
ATmega128RFA1
encryption operation. However, the initial AES key written to the security module in
advance of an AES run is not modified during an AES operation. This initial key is used
for the next AES run even if it cannot be read from AES_KEY register. Note that the
AES_KEY register is cleared when entering the radio transceiver SLEEP state.
Bit 7:0 – AES_KEY7:0 - AES Encryption/Decryption Key Buffer
These bits represent the data buffer for the AES Encryption/Decryption key.
9.12.5 TRX_STATUS – Transceiver Status Register
Bit
7
6
5
4
NA ($141)
CCA_DONE
CCA_STATUS
TST_STATUS
TRX_STATUS4
TRX_STATUS
Read/Write
R
Initial Value
0
Bit
3
2
1
0
NA ($141)
TRX_STATUS3
TRX_STATUS2
TRX_STATUS1
TRX_STATUS0
TRX_STATUS
Read/Write
R
Initial Value
0
This read-only register signals the present state of the radio transceiver as well as the
status of the CCA operation. A state change is initiated by writing a state transition
command to the TRX_CMD bits of register TRX_STATE. The register is not accessible
in SLEEP state.
Bit 7 – CCA_DONE - CCA Algorithm Status
This bit indicates if a CCA request is completed. This is also indicated by a
TRX24_CCA_ED_DONE interrupt. Note that register bit CCA_DONE is cleared in
response to a CCA_REQUEST.
Table 9-30 CCA_DONE Register Bits
Register Bits
Value
Description
0
CCA calculation not finished
CCA_DONE
1
CCA calculation finished
Bit 6 – CCA_STATUS - CCA Status Result
The result of the CCA measurement is available in register bit CCA_STATUS after a
CCA request is completed. Note that register bit CCA_STATUS is cleared in response
to a CCA_REQUEST.
Table 9-31 CCA_STATUS Register Bits
Register Bits
Value
Description
0
Channel indicated as busy.
CCA_STATUS
1
Channel indicated as idle.
Bit 5 – TST_STATUS - Test mode status
This bit is reserved for internal use. It indicates the status of the test mode.
Table 9-32 TST_STATUS Register Bits
Register Bits
Value
Description
0
Test mode is disabled.
TST_STATUS
1
Test mode is active.
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