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| 型號： | MB9BF505RPMC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120 |
| 文件頁數(shù)： | 10/120頁 |
| 文件大?。?/td> | 1277K |
| 代理商： | MB9BF505RPMC |
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107
8266D-MCU Wireless-06/12
ATmega128RFA1
procedures set the register bits to TRAC_STATUS = 7 (INVALID) when it is started. Not
all status values are used in both RX_AACK and TX_ARET transactions. In TX_ARET
the status SUCCESS_DATA_PENDING indicates a successful reception of an ACK
frame
with
frame
pending
bit
set
to
1.
In
RX_AACK
the
status
SUCCESS_WAIT_FOR_ACK indicates an ACK frame is about to sent in RX_AACK
slotted acknowledgment. Slotted acknowledgment operation must be enabled with the
SLOTTED_OPERATION bit of register XAH_CTRL_0. The application software must
set the SLPTR bit of register TRXPWR at the next back-off slot boundary in order to
initiate a transmission of the ACK frame. For details refer to IEEE 802.15.4-2006,
chapter 5.5.4.1. Values not listed in the following table are reserved.
Table 9-34 TRAC_STATUS Register Bits
Register Bits
Value
Description
0
SUCCESS (RX_AACK, TX_ARET)
1
SUCCESS_DATA_PENDING (TX_ARET)
2
SUCCESS_WAIT_FOR_ACK (RX_AACK)
3
CHANNEL_ACCESS_FAILURE (TX_ARET)
5
NO_ACK (TX_ARET)
TRAC_STATUS2:0
7
INVALID (RX_AACK, TX_ARET)
Bit 4:0 – TRX_CMD4:0 - State Control Command
A write access to register bits TRX_CMD initiates a state transition of the radio
transceiver towards the new state as defined by the write access. Do not try to initiate a
further
state
change
while
the
radio
transceiver
is
in
STATE_TRANSITION_IN_PROGRESS
state
(see
TRX_STATUS
register).
FORCE_PLL_ON
is
not
valid
for
the
SLEEP
state
as
well
as
during
STATE_TRANSITION_IN_PROGRESS towards the SLEEP state. Values not listed in
the following table are reserved and mapped to NOP.
Table 9-35 TRX_CMD Register Bits
Register Bits
Value
Description
0x00
NOP
0x02
TX_START
0x03
FORCE_TRX_OFF
0x04
FORCE_PLL_ON
0x06
RX_ON
0x08
TRX_OFF
0x09
PLL_ON (TX_ON)
0x16
RX_AACK_ON
TRX_CMD4:0
0x19
TX_ARET_ON
9.12.7 TRX_CTRL_0 – Reserved
Bit
7
6
5
4
3
2
1
0
NA ($143)
Res7
Res6
Res5
Res4
Res3
Res2
Res1
Res0
TRX_CTRL_0
Read/Write
RW
Initial Value
0
1
0
1
This register is reserved for future use.
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