參數(shù)資料
型號： MB9BF505RPMC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP120
封裝： 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120
文件頁數(shù)： 120/120頁
文件大?。?/td> 1277K
代理商： MB9BF505RPMC
99
8266D-MCU Wireless-06/12
ATmega128RFA1
for the PRBS mode. The SHR and the PHR are not transmitted. The transmission starts
with the PSDU data and is repeated continuously.
9.9.2 Configuration
All register configurations shall be setup as follows before enabling Continuous
Transmission Test Mode:
TX channel setting (optional);
TX output power setting (optional);
Mode selection (PRBS / CW);
An access to the registers TST_CTRL_DIGI and PART_NUM enables the Continuous
Transmission Test Mode.
The transmission is started by enabling the PLL (TRX_CMD = PLL_ON) and writing the
TX_START command to register TRX_STATE.
Even for CW signal transmission it is required to write valid PSDU data (see chapter
"Frame Buffer Access " on page 33) to the Frame Buffer. The first byte defines the
frame length information. The frame length has to match to the length of the pattern
stored in the frame buffer. For PRBS mode it is recommended to use a frame of
maximum length.
The detailed programming sequence is shown in Table 9-26 below. The column R/W
informs about writing (W) or reading (R) a register or the Frame Buffer.
Table 9-26. Continuous Transmission Programming Sequence
Step
Action
Register
R/
W
Value
Description
1
RESET
Reset the transceiver
2
Register Access
IRQ_MASK
W
0x01
Set IRQ mask register, enable
PLL_LOCK interrupt and set
global AVR IRQ enable
3
Register Access
TRX_CTRL_1
W
0x00
Disable TX_AUTO_CRC_ON
4
Register Access
TRX_STATE
W
0x03
Set radio transceiver state
TRX_OFF
5
Register Access
PHY_CC_CCA
W
0x33
Set IEEE 802.15.4 CHANNEL,
e.g. 19
6
Register Access
PHY_TX_PWR
W
0x00
Set TX output power, e.g. to Pmax
7
Register Access
TRX_STATUS
R
0x08
Verify TRX_OFF state
8
Register Access
TST_CTRL_DIGI
W
0x0F
Enable Continuous Transmission
Test Mode – step # 1
9
(1)
Register Access
TRX_CTRL_2
W
0x03
Enable High Data Rate Mode, 2
Mb/s
10
(1)
Register Access
RX_CTRL
W
0xA7
Configure High Data Rate Mode
11
(2)
Frame Buffer
Write Access
W
Write PSDU data (even for CW
mode), refer to Table 9-27 on
12
Register Access
PART_NUM
W
0x54
Enable Continuous Transmission
Test Mode – step # 2
13
Register Access
PART_NUM
W
0x46
Enable Continuous Transmission
Test Mode – step # 3
14
Register Access
TRX_STATE
W
0x09
Enable PLL_ON state
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