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| 型號(hào)： | MB9BF505RPMC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120 |
| 文件頁(yè)數(shù)： | 119/120頁(yè) |
| 文件大?。?/td> | 1277K |
| 代理商： | MB9BF505RPMC |
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98
8266D-MCU Wireless-06/12
ATmega128RFA1
register. Setting bit AES_REQUEST = 1 (AES_CTRL register) as described in section
"Security Operation Modes" on page 96 starts the first encryption. This causes the next
128 bits of plain text data to be XORed with the previous cipher text data, see Figure 9-
According to IEEE 802.15.4 the input for the very first CBC operation has to be
prepared by a XOR operation of the plain text with the initialization vector (IV). The
value of the initialization vector is 0. However any other initialization vector can be
applied for non-compliant usage. This operation has to be prepared by the application
software.
Note that the MIC algorithm of the IEEE 802.15.4-2006 standard requires CBC mode
encryption only because it implements a one-way hash function.
The status of the security processing is indicated by register AES_STATUS. After a
AES processing time of 24 s the register bit AES_DONE changes to 1 (register
AES_STATUS) indicating that the security operation has finished (see "Digital Interface
The end of the AES processing can also be indicated by the AES_READY Interrupt.
The bit AES_ER of register AES_STATUS is set if the operation has finished with an
error. Otherwise this bit is zero but AES_DONE is ‘1’.
9.8.8.5 AES Interrupt Handling
The AES Interrupt handling is slightly different from all other IRQ’s. If the AES_IM Bit
(AES_CTRL Register) and the global interrupt enable flag is set, the AES core can
generate an AES Ready Interrupt (AES_READY). If the IRQ is issued, the
AES_STATUS register must be read to check the finish status of the last operation. If
AES_DONE is set, the last AES operation finished successfully. If AES_ER is set, an
error occurred during the last operation. The AES_ER flag is cleared automatically
during the read access to the AES_STATUS register. The AES_DONE flag is cleared
during the next read or write access to the AES_STATE (AES data) register.
The two status flags must be cleared before a new Interrupt can be issued.
If AES_IM is not set, the processing status can be polled by software (AES_STATUS
register), but no Interrupt occurs.
9.9 Continuous Transmission Test Mode
9.9.1 Overview
The 2.4GHz transceiver offers a Continuous Transmission Test Mode to support final
application / production tests as well as certification tests. In this test mode the radio
transceiver transmits continuously a previously transferred frame (PRBS mode) or a
continuous wave signal (CW mode).
In CW mode two different signal frequencies per channel can be transmitted:
f1 = fCH + 0.5 MHz
f2 = fCH - 0.5 MHz
Here fCH is the channel center frequency programmed by register PHY_CC_CCA.
Note that in CW mode it is not possible to transmit a RF signal directly on the channel
center frequency. PSDU data in the Frame Buffer must contain at least a valid PHR
(see section "Introduction – IEEE 802.15.4-2006 Frame Format" on page 63). It is
recommended to use a frame of maximum length (127 bytes) and arbitrary PSDU data
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