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參數(shù)資料
| 型號： | MB95F564KPF-G-JNE2 |
| 廠商： | Fujitsu Semiconductor America Inc |
| 文件頁數(shù)： | 65/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 20KB FLASH 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,225 |
| 系列： | 8FX MB95560H |
| 核心處理器： | F²MC-8FX |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | LIN，UART/USART |
| 外圍設(shè)備： | LVD. POR，PWM，WDT |
| 輸入/輸出數(shù)： | 17 |
| 程序存儲器容量： | 20KB（20K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 496 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 6x8/10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 托盤 |
| 其它名稱： | 865-1239 |
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dsPIC30F4011/4012
DS70135G-page 68
2010 Microchip Technology Inc.
FIGURE 9-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER)
9.1
Timer Gate Operation
The 16-bit timer can be placed in the Gated Time Accu-
mulation mode. This mode allows the internal TCY to
increment the respective timer when the gate input
signal (T1CK pin) is asserted high. Control bit, TGATE
(T1CON<6>), must be set to enable this mode. The
timer must be enabled (TON = 1) and the timer clock
source set to internal (TCS = 0).
When the CPU goes into the Idle mode, the timer will
stop incrementing unless TSIDL = 0. If TSIDL = 1, the
timer will resume the incrementing sequence upon
termination of the CPU Idle mode.
9.2
Timer Prescaler
The input clock (FOSC/4 or external clock) to the 16-bit
Timer has a prescale option of 1:1, 1:8, 1:64 and 1:256
selected by control bits, TCKPS<1:0> (T1CON<5:4>).
The prescaler counter is cleared when any of the
following occurs:
A write to the TMR1 register
Clearing of the TON bit (T1CON<15>)
A device Reset, such as a POR and BOR
However, if the timer is disabled (TON = 0), then the
timer prescaler cannot be reset since the prescaler
clock is halted.
The TMR1 register is not cleared when the T1CON
register is written. It is cleared by writing to the TMR1
register.
9.3
Timer Operation During Sleep
Mode
During CPU Sleep mode, the timer will operate if:
The timer module is enabled (TON = 1) and
The timer clock source is selected as external
(TCS = 1) and
The TSYNC bit (T1CON<2>) is asserted to a logic
‘0’, which defines the external clock source as
asynchronous
When all three conditions are true, the timer will
continue to count up to the Period register and be reset
to 0x0000.
When a match between the timer and the Period regis-
ter occurs, an interrupt can be generated if the
respective timer interrupt enable bit is asserted.
TON
Sync
SOSCI
SOSCO/
PR1
T1IF
Equal
Comparator x 16
TMR1
Reset
LPOSCEN
Event Flag
1
0
TSYNC
Q
QD
CK
TGATE
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TGATE
TCY
1
0
T1CK
TCS
1 x
0 1
TG
A
T
E
0 0
Gate
Sync
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