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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MB95F564KPF-G-JNE2 |
| 寤犲晢锛� | Fujitsu Semiconductor America Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 44/84闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU 8BIT 20KB FLASH 20TSSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1,225 |
| 绯诲垪锛� | 8FX MB95560H |
| 鏍稿績铏曠悊鍣細 | F²MC-8FX |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 16MHz |
| 閫ｉ€氭€э細 | LIN锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | LVD. POR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 17 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 20KB锛�20K x 8锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 496 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.4 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 6x8/10b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 20-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 鍖呰锛� | 鎵樼洡 |
| 鍏跺畠鍚嶇ū锛� | 865-1239 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�鐣�(d膩ng)鍓嶇44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�
MB95560H/570H/580H Series
DS702-00010-2v0-E
49
(Continued)
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA =
40掳C to + 85掳C)
*: The external clock signal is input to X0 and the inverted external clock signal to X1.
Parameter
Symbol Pin name Condition
Value
Unit
Remarks
Min
Typ
Max
Clock cycle
time
tHCYL
X0, X1
鈥�
61.5
鈥�
1000
ns
When the main oscillation
circuit is used
X0
X1 : open
83.4
鈥�
1000
ns
When an external clock is
used
X0, X1
*
30.8
鈥�
1000
ns
tLCYL
X0A, X1A
鈥�
30.5
鈥�
s
When the subclock is used
Input clock
pulse width
tWH1
tWL1
X0
X1 : open
33.4
鈥�
ns
When an external clock is
used, the duty ratio should
range between 40% and 60%.
X0, X1
*
14.4
鈥�
ns
tWH2
tWL2
X0A
鈥�
15.2
鈥�
s
Input clock rise
time and fall
time
tCR
tCF
X0
X1 : open
鈥�
5
ns
When an external clock is
used
X0, X1
*
鈥�
5
ns
CR oscillation
start time
tCRHWK
鈥�
50
s
When the main CR clock is
used
tCRLWK
鈥�
30
s
When the sub-CR clock is
used
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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