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參數(shù)資料
型號(hào)： MB95F564KPF-G-JNE2
廠商： Fujitsu Semiconductor America Inc
文件頁(yè)數(shù)： 47/84頁(yè)
文件大?。?/td> 0K
描述： IC MCU 8BIT 20KB FLASH 20TSSOP
標(biāo)準(zhǔn)包裝： 1,225
系列： 8FX MB95560H
核心處理器： F²MC-8FX
芯體尺寸： 8-位
速度： 16MHz
連通性： LIN，UART/USART
外圍設(shè)備： LVD. POR，PWM，WDT
輸入/輸出數(shù)： 17
程序存儲(chǔ)器容量： 20KB（20K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 496 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x8/10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
包裝： 托盤
其它名稱： 865-1239
MB95560H/570H/580H Series
DS702-00010-2v0-E
51
(2) Source Clock / Machine Clock
(VCC = 5.0 V
± 10%, VSS = 0.0 V, TA = 40°C to + 85°C)
*1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio
select bits (SYCC:DIV1, DIV0). This source clock is divided to become a machine clock according to the
division ratio set by the machine clock division ratio select bits (SYCC
:DIV1, DIV0). In addition, a source
clock can be selected from the following.
Main clock divided by 2
PLL multiplication of main clock (Select a multiplier from 2, 2.5, 3 and 4.)
Main CR clock
Subclock divided by 2
Sub-CR clock divided by 2
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
Source clock (no division)
Source clock divided by 4
Source clock divided by 8
Source clock divided by 16
Parameter
Symbol
Pin
name
Value
Unit
Remarks
Min
Typ
Max
Source clock
cycle time*1
tSCLK
—
61.5
—
2000
ns
When the main external clock is used
Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
62.5
—
1000
ns
When the main CR clock is used
Min: FCRH = 4 MHz, multiplied by 4
Max: FCRH = 4 MHz, divided by 4
—61—
s
When the sub-oscillation clock is used
FCL = 32.768 kHz, divided by 2
—20—
s
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
Source clock
frequency
FSP
—
0.5
—
16.25
MHz When the main oscillation clock is used
—
4
—
MHz When the main CR clock is used
FSPL
—
16.384
—
kHz When the sub-oscillation clock is used
—
50
—
kHz
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
Machine clock
cycle time*2
(minimum
instruction
execution
time)
tMCLK
—
61.5
—
32000
ns
When the main oscillation clock is used
Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
250
—
1000
ns
When the main CR clock is used
Min: FSP = 4 MHz, no division
Max: FSP = 4 MHz, divided by 4
61
—
976.5
s
When the sub-oscillation clock is used
Min: FSPL = 16.384 kHz, no division
Max: FSPL = 16.384 kHz, divided by 16
20
—
320
s
When the sub-CR clock is used
Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
Machine clock
frequency
FMP
—
0.031
—
16.25
MHz When the main oscillation clock is used
0.25
—
16
MHz When the main CR clock is used
FMPL
1.024
—
16.384
kHz When the sub-oscillation clock is used
3.125
—
50
kHz
When the sub-CR clock is used
FCRL = 100 kHz
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