
2010 Microchip Technology Inc.
DS70135G-page 61
dsPIC30F4011/4012
8.0
I/O PORTS
All of the device pins (except VDD, VSS, MCLR and
OSC1/CLKI) are shared between the peripherals and
the parallel I/O ports.
All I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.
8.1
Parallel I/O (PIO) Ports
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
may be read, but the output driver for the Parallel Port
bit will be disabled. If a peripheral is enabled, but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
All port pins have three registers directly associated
with the operation of the port pin. The Data Direction
register (TRISx) determines whether the pin is an input
or an output. If the Data Direction register bit is a ‘1’,
then the pin is an input. All port pins are defined as
inputs after a Reset. Reads from the latch (LATx), read
the latch. Writes to the latch, write the latch (LATx).
Reads from the port (PORTx), read the port pins and
writes to the port pins, write the latch (LATx).
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers and the port pin will read as zeros.
When a pin is shared with another peripheral or func-
tion that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs. An example is the
INT4 pin.
The format of the registers for PORTx are shown in
The TRISx (Data Direction) register controls the direc-
tion of the pins. The LATx register supplies data to the
outputs and is readable/writable. Reading the PORTx
register yields the state of the input pins, while writing
to the PORTx register modifies the contents of the
LATx register.
A parallel I/O (PIO) port that shares a pin with a periph-
eral is, in general, subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pad cell.
Figure 8-2 shows how ports are shared
with other peripherals and the associated I/O cell (pad)
show the formats of the registers for the shared ports,
PORTB through PORTG.
FIGURE 8-1:
BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals,
register
descriptions
and
general device functionality, refer to the
dsPIC30F
Family
Reference
Manual
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
Q
D
CK
WR LAT +
TRIS Latch
I/O Pad
WR PORT
Data Bus
Q
D
CK
Data Latch
Read LAT
Read PORT
Read TRIS
WR TRIS
I/O Cell
Dedicated Port Module