參數(shù)資料
型號(hào)： MB91101APF-G-JNE1
廠(chǎng)商： FUJITSU LTD
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù)： 79/100頁(yè)
文件大?。?/td> 2083K
代理商： MB91101APF-G-JNE1
MB91101 Series
8
DS07-16301-6E
*1: FPT-100P-M20
*2: FPT-100P-M06
(Continued)
Pin no.
Pin name
Circuit
type
Description
LQFP*1
QFP*2
14
CS1L
F
CASL output for DRAM bank 1
Refer to the DRAM interface for details.
PB5
Can be configured as a port when CS1L and DREQ2 are not used.
DREQ2
External transfer request input pin for DMA
This pin is used for input when external trigger is selected to cause
DMAC operation, and it is necessary to disable output for other
functions from this pin unless such output is made intentionally.
25
CS1H
F
CASH output for DRAM bank 1
Refer to the DRAM interface for details.
PB6
Can be configured as a port when CS1H and DACK2 are not used.
DACK2
External transfer request acknowledge output pin for DMAC (ch. 2)
This function is available when transfer request output for DMAC is
enabled.
36
DW1
F
WE output for DRAM bank 1 (“L” active)
Refer to the DRAM interface for details.
PB7
Can be configured as a port when DW1 is not used.
16 to 18
19 to 21
MD0 to
MD2
G
Mode pins 0 to 2
MCU basic operation mode is set by these pins.
Directly connect these pins with VCC or VSS for use.
92
95
X0
A
Clock (oscillator) input
91
94
X1
A
Clock (oscillator) output
14
17
RST
B
External reset input
13
16
HST
H
Hardware standby input (“L” active)
12
15
NMI
H
NMI (non-maskable interrupt pin) input (“L” active)
95,
94
98,
97
INT0,
INT1
F
External interrupt request input pins
These pins are used for input during corresponding interrupt is en-
abled, and it is necessary to disable output for other functions from
these pins unless such output is made intentionally.
PE0,
PE1
Can be configured as I/O ports when INT0, INT1 are not used.
89
92
INT2
F
External interrupt request input pin
This pin is used for input during corresponding interrupt is enabled,
and it is necessary to disable output for other functions from this pin
unless such output is made intentionally.
SC1
Clock I/O pin for UART1
Clock output is available when clock output of UART1 is enabled.
PE2
Can be configured as the I/O port when INT2 and SC1 are not used.
This function is available when UART1 clock output is disabled.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB91101APFR-G-JNE1 制造商:FUJITSU 功能描述:
MB91101APFV 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:32-bit RISC Microcontroller
MB91106 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:32-bit RISC Microcontroller
MB91106PF 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:32-bit RISC Microcontroller
MB91106PFV 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:32-bit RISC Microcontroller
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