參數(shù)資料
型號(hào)： MB91101APF-G-JNE1
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù)： 73/100頁(yè)
文件大?。?/td> 2083K
代理商： MB91101APF-G-JNE1
MB91101 Series
74
DS07-16301-6E
(5) Normal Bus Access Read/Write Operation
(VCC5 = 5.0 V
±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40
°C to +70°C)
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
*1: When bus timing is delayed by automatic wait insertion or RDY input, add (tCYC
× extended cycle number)
to this rating.
*2: Rating at a gear cycle of
× 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8,
respectively.
Equation: (2 – n/2)
× tCYC – 25
Parameter
Symbol
Pin name
Condition
Value
Unit
Remarks
Min
Max
CS0 to CS5 delay time
tCHCSL
CLK,
CS0 to CS5
—
—15
ns
tCHCSH
CLK,
CS0 to CS5
—15
ns
Address delay time
tCHAV
CLK,
A24 to A00
—15
ns
Data delay time
tCHDV
CLK,
D31 to D16
—15
ns
RD delay time
tCLRL
CLK, RD
—6
ns
tCLRH
CLK, RD
—6
ns
WR0, WR1 delay time
tCLWL
CLK,
WR0, WR1
—6
ns
tCLWH
CLK,
WR0, WR1
—6
ns
Valid address
→ valid data
input time
tAVDV
A24 to A00,
D31 to D16
—
3/2
× tCYC
– 25
ns
*1
*2
RD
↓→ valid data input time tRLDV
RD,
D31 to D16
—tCYC – 10
ns
*1
Data set up
→ RD ↑ time
tDSRH
RD,
D31 to D16
10
—
ns
RD
↑→ data hold time
tRHDX
RD,
D31 to D16
0—
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB91101APFR-G-JNE1 制造商:FUJITSU 功能描述:
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MB91106PFV 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit RISC Microcontroller
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